1 // SPDX-License-Identifier: ISC
3 * Device Tree file for Intel XScale Network Processors
4 * in the IXP 4xx series.
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/gpio/gpio.h>
14 compatible = "simple-bus";
15 interrupt-parent = <&intcon>;
18 * The IXP4xx expansion bus is a set of up to 7 each up to 16MB
19 * windows in the 256MB space from 0x50000000 to 0x5fffffff.
22 /* compatible and reg filled in by per-soc device tree */
26 ranges = <0 0x0 0x50000000 0x01000000>,
27 <1 0x0 0x51000000 0x01000000>,
28 <2 0x0 0x52000000 0x01000000>,
29 <3 0x0 0x53000000 0x01000000>,
30 <4 0x0 0x54000000 0x01000000>,
31 <5 0x0 0x55000000 0x01000000>,
32 <6 0x0 0x56000000 0x01000000>,
33 <7 0x0 0x57000000 0x01000000>;
34 dma-ranges = <0 0x0 0x50000000 0x01000000>,
35 <1 0x0 0x51000000 0x01000000>,
36 <2 0x0 0x52000000 0x01000000>,
37 <3 0x0 0x53000000 0x01000000>,
38 <4 0x0 0x54000000 0x01000000>,
39 <5 0x0 0x55000000 0x01000000>,
40 <6 0x0 0x56000000 0x01000000>,
41 <7 0x0 0x57000000 0x01000000>;
44 qmgr: queue-manager@60000000 {
45 compatible = "intel,ixp4xx-ahb-queue-manager";
46 reg = <0x60000000 0x4000>;
47 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
51 /* compatible filled in by per-soc device tree */
52 reg = <0xc0000000 0x1000>;
53 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
54 <9 IRQ_TYPE_LEVEL_HIGH>,
55 <10 IRQ_TYPE_LEVEL_HIGH>;
59 bus-range = <0x00 0xff>;
64 * 64MB 32bit non-prefetchable memory 0x48000000-0x4bffffff
65 * done in 4 chunks of 16MB each.
67 <0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
68 /* 64KB I/O space at 0x4c000000 */
69 <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
72 * This needs to map to the start of physical memory so
73 * PCI devices can see all (hopefully) memory. This is done
74 * using 4 1:1 16MB windows, so the RAM should not be more than
75 * 64 MB for this to work. If your memory is anywhere else
76 * than at 0x0 you need to alter this.
79 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
81 #interrupt-cells = <1>;
82 interrupt-map-mask = <0xf800 0 0 7>;
83 /* Each unique DTS using PCI must specify the swizzling */
86 uart0: serial@c8000000 {
87 compatible = "intel,xscale-uart";
88 reg = <0xc8000000 0x1000>;
90 * The reg-offset and reg-shift is a side effect
91 * of running the platform in big endian mode.
95 interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
96 clock-frequency = <14745600>;
100 uart1: serial@c8001000 {
101 compatible = "intel,xscale-uart";
102 reg = <0xc8001000 0x1000>;
104 * The reg-offset and reg-shift is a side effect
105 * of running the platform in big endian mode.
109 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
110 clock-frequency = <14745600>;
114 gpio0: gpio@c8004000 {
115 compatible = "intel,ixp4xx-gpio";
116 reg = <0xc8004000 0x1000>;
119 interrupt-controller;
120 #interrupt-cells = <2>;
123 intcon: interrupt-controller@c8003000 {
125 * Note: no compatible string. The subvariant of the
126 * chip needs to define what version it is. The
127 * location of the interrupt controller is fixed in
128 * memory across all variants.
130 reg = <0xc8003000 0x100>;
131 interrupt-controller;
132 #interrupt-cells = <2>;
136 compatible = "intel,ixp4xx-timer";
137 reg = <0xc8005000 0x100>;
138 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
142 compatible = "intel,ixp4xx-network-processing-engine";
143 reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
145 /* NPE-C contains a crypto accelerator */
147 compatible = "intel,ixp4xx-crypto";
148 intel,npe-handle = <&npe 2>;
149 queue-rx = <&qmgr 30>;
150 queue-txready = <&qmgr 29>;
154 /* This is known as EthB */
156 compatible = "intel,ixp4xx-ethernet";
157 reg = <0xc8009000 0x1000>;
159 /* Dummy values that depend on firmware */
160 queue-rx = <&qmgr 3>;
161 queue-txready = <&qmgr 20>;
162 intel,npe-handle = <&npe 1>;
165 /* This is known as EthC */
167 compatible = "intel,ixp4xx-ethernet";
168 reg = <0xc800a000 0x1000>;
170 /* Dummy values that depend on firmware */
171 queue-rx = <&qmgr 0>;
172 queue-txready = <&qmgr 0>;
173 intel,npe-handle = <&npe 2>;
176 /* This is known as EthA */
178 compatible = "intel,ixp4xx-ethernet";
179 reg = <0xc800c000 0x1000>;
182 /* Dummy values that depend on firmware */
183 queue-rx = <&qmgr 0>;
184 queue-txready = <&qmgr 0>;