1 // SPDX-License-Identifier: ISC
3 * Device Tree file for Gateworks IXP43x-based Cambria GW2358
8 #include "intel-ixp43x.dtsi"
11 model = "Gateworks Cambria GW2358";
12 compatible = "gateworks,gw2358", "intel,ixp43x";
18 device_type = "memory";
19 reg = <0x00000000 0x8000000>;
23 bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
24 stdout-path = "uart0:115200n8";
32 compatible = "gpio-leds";
34 label = "gw2358:green:LED";
35 gpios = <&pld1 0 GPIO_ACTIVE_LOW>;
37 linux,default-trigger = "heartbeat";
43 compatible = "i2c-gpio";
44 sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
45 scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
50 compatible = "adi,ad7418";
54 compatible = "dallas,ds1672";
58 compatible = "atmel,24c08";
65 compatible = "gateworks,pld-gpio";
70 /* This PLD just handles the LED and user button */
72 compatible = "gateworks,pld-gpio";
82 compatible = "intel,ixp4xx-flash", "cfi-flash";
85 * 32 MB of Flash in 0x20000 byte blocks
88 reg = <0x00000000 0x2000000>;
91 compatible = "redboot-fis";
92 /* Eraseblock at 0x1fe0000 */
93 fis-index-block = <0xff>;
102 * In the boardfile for the Cambria from OpenWRT the interrupts
103 * are assigned one per IDSEL, so all 4 interrupts from IDSEL
104 * 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2
105 * connected to IRQ 10 etc. I find this highly unlikely so I
106 * have instead assumed that they are rotated (swizzled) like
107 * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc.
111 <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
112 <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
113 <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
114 <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
116 <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
117 <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
118 <0x1000 0 0 3 &gpio0 8 3>, /* INT C on slot 2 is irq 8 */
119 <0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */
121 <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
122 <0x1800 0 0 2 &gpio0 8 3>, /* INT B on slot 3 is irq 8 */
123 <0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */
124 <0x1800 0 0 4 &gpio0 10 3>, /* INT D on slot 3 is irq 10 */
126 <0x2000 0 0 1 &gpio0 8 3>, /* INT A on slot 3 is irq 8 */
127 <0x2000 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
128 <0x2000 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
129 <0x2000 0 0 4 &gpio0 9 3>, /* INT D on slot 3 is irq 9 */
131 <0x3000 0 0 1 &gpio0 10 3>, /* INT A on slot 3 is irq 10 */
132 <0x3000 0 0 2 &gpio0 9 3>, /* INT B on slot 3 is irq 9 */
133 <0x3000 0 0 3 &gpio0 8 3>, /* INT C on slot 3 is irq 8 */
134 <0x3000 0 0 4 &gpio0 11 3>, /* INT D on slot 3 is irq 11 */
136 <0x7800 0 0 1 &gpio0 8 3>, /* INT A on slot 3 is irq 8 */
137 <0x7800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
138 <0x7800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
139 <0x7800 0 0 4 &gpio0 9 3>; /* INT D on slot 3 is irq 9 */
144 queue-rx = <&qmgr 4>;
145 queue-txready = <&qmgr 21>;
147 phy-handle = <&phy1>;
150 #address-cells = <1>;
153 phy1: ethernet-phy@1 {
157 phy2: ethernet-phy@2 {
165 queue-rx = <&qmgr 2>;
166 queue-txready = <&qmgr 19>;
168 phy-handle = <&phy2>;
169 intel,npe-handle = <&npe 0>;