1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Device Tree Source for TQ Systems TQMa7D board on MBa7 carrier board.
5 * Copyright (C) 2016 TQ Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
7 * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
12 #include "imx7d-tqma7.dtsi"
13 #include "imx7-mba7.dtsi"
16 model = "TQ Systems TQMa7D board on MBa7 carrier board";
17 compatible = "tq,imx7d-mba7", "tq,imx7d-tqma7", "fsl,imx7d";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_enet2>;
23 phy-mode = "rgmii-id";
24 phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
25 phy-reset-duration = <1>;
26 phy-supply = <®_fec2_pwdn>;
27 phy-handle = <ðphy2_0>;
35 ethphy2_0: ethernet-phy@0 {
36 compatible = "ethernet-phy-ieee802.3-c22";
38 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
39 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
40 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
41 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_hog_mba7_1>;
50 pinctrl_enet2: enet2grp {
52 MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02
53 MX7D_PAD_SD2_WP__ENET2_MDC 0x00
54 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71
55 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71
56 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71
57 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71
58 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71
59 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71
60 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79
61 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79
62 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79
63 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79
64 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79
65 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79
66 /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
67 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070
68 /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
69 MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078
73 pinctrl_pcie: pciegrp {
76 MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70
78 MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70
80 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70
86 pinctrl_usbotg2: usbotg2grp {
88 MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c
89 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_pcie>;
97 /* 1.5V logically from 3.3V */
98 /* probe deferral not supported */
99 /* pcie-bus-supply = <®_mpcie_1v5>; */
100 reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_usbotg2>;
107 vbus-supply = <®_usb_otg2_vbus>;