arch/arm/boot/dts/imx7-mba7.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR X11
   2 /*
   3  * Device Tree Include file for TQ Systems MBa7 carrier board.
   4  *
   5  * Copyright (C) 2016 TQ Systems GmbH
   6  * Author: Markus Niebel <Markus.Niebel@tq-group.com>
   7  * Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
   8  *
   9  * Note: This file does not include nodes for all peripheral devices.
  10  * As device driver coverage increases additional nodes can be added.
  11  */
  12
  13 #include <dt-bindings/input/input.h>
  14 #include <dt-bindings/net/ti-dp83867.h>
  15
  16 / {
  17         beeper {
  18                 compatible = "gpio-beeper";
  19                 gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>;
  20         };
  21
  22         chosen {
  23                 stdout-path = &uart6;
  24         };
  25
  26         gpio_buttons: gpio-keys {
  27                 compatible = "gpio-keys";
  28
  29                 button-0 {
  30                         /* #SWITCH_A */
  31                         label = "S11";
  32                         linux,code = <KEY_1>;
  33                         gpios = <&pca9555 13 GPIO_ACTIVE_LOW>;
  34                 };
  35
  36                 button-1 {
  37                         /* #SWITCH_B */
  38                         label = "S12";
  39                         linux,code = <KEY_2>;
  40                         gpios = <&pca9555 14 GPIO_ACTIVE_LOW>;
  41                 };
  42
  43                 button-2 {
  44                         /* #SWITCH_C */
  45                         label = "S13";
  46                         linux,code = <KEY_3>;
  47                         gpios = <&pca9555 15 GPIO_ACTIVE_LOW>;
  48                 };
  49         };
  50
  51         gpio-leds {
  52                 compatible = "gpio-leds";
  53
  54                 led1 {
  55                         label = "led1";
  56                         gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>;
  57                         linux,default-trigger = "default-on";
  58                 };
  59
  60                 led2 {
  61                         label = "led2";
  62                         gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>;
  63                         linux,default-trigger = "heartbeat";
  64                 };
  65         };
  66
  67         reg_sd1_vmmc: regulator-sd1-vmmc {
  68                 compatible = "regulator-fixed";
  69                 regulator-name = "VCC3V3_SD1";
  70                 regulator-min-microvolt = <3300000>;
  71                 regulator-max-microvolt = <3300000>;
  72                 regulator-always-on;
  73         };
  74
  75         reg_fec1_pwdn: regulator-fec1-pwdn {
  76                 compatible = "regulator-fixed";
  77                 regulator-name = "PWDN_FEC1";
  78                 regulator-min-microvolt = <3300000>;
  79                 regulator-max-microvolt = <3300000>;
  80                 regulator-always-on;
  81                 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  82                 enable-active-high;
  83         };
  84
  85         reg_fec2_pwdn: regulator-fec2-pwdn {
  86                 compatible = "regulator-fixed";
  87                 regulator-name = "PWDN_FEC2";
  88                 regulator-min-microvolt = <3300000>;
  89                 regulator-max-microvolt = <3300000>;
  90                 regulator-always-on;
  91                 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
  92                 enable-active-high;
  93         };
  94
  95         reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  96                 compatible = "regulator-fixed";
  97                 regulator-name = "VBUS_USBOTG1";
  98                 regulator-min-microvolt = <5000000>;
  99                 regulator-max-microvolt = <5000000>;
 100                 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 101                 enable-active-high;
 102         };
 103
 104         reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
 105                 compatible = "regulator-fixed";
 106                 regulator-name = "VBUS_USBOTG2";
 107                 regulator-min-microvolt = <5000000>;
 108                 regulator-max-microvolt = <5000000>;
 109                 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 110                 enable-active-high;
 111         };
 112
 113         reg_mpcie_1v5: regulator-mpcie-1v5 {
 114                 compatible = "regulator-fixed";
 115                 regulator-name = "VCC1V5_MPCIE";
 116                 regulator-min-microvolt = <1500000>;
 117                 regulator-max-microvolt = <1500000>;
 118                 gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>;
 119                 enable-active-high;
 120                 regulator-always-on;
 121         };
 122
 123         reg_mpcie_3v3: regulator-mpcie-3v3 {
 124                 compatible = "regulator-fixed";
 125                 regulator-name = "VCC3V3_MPCIE";
 126                 regulator-min-microvolt = <3300000>;
 127                 regulator-max-microvolt = <3300000>;
 128                 gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>;
 129                 enable-active-high;
 130                 regulator-always-on;
 131         };
 132
 133         reg_mba_12v0: regulator-mba-12v0 {
 134                 compatible = "regulator-fixed";
 135                 regulator-name = "VCC12V0_MBA7";
 136                 regulator-min-microvolt = <12000000>;
 137                 regulator-max-microvolt = <12000000>;
 138                 gpio = <&pca9555 11 GPIO_ACTIVE_HIGH>;
 139                 enable-active-high;
 140         };
 141
 142         reg_lvds_transmitter: regulator-lvds-transmitter {
 143                 compatible = "regulator-fixed";
 144                 regulator-name = "#SHTDN_LVDS";
 145                 regulator-min-microvolt = <3300000>;
 146                 regulator-max-microvolt = <3300000>;
 147                 gpio = <&pca9555 1 GPIO_ACTIVE_HIGH>;
 148                 enable-active-high;
 149         };
 150
 151         reg_vref_1v8: regulator-vref-1v8 {
 152                 compatible = "regulator-fixed";
 153                 regulator-name = "VCC1V8_REF";
 154                 regulator-min-microvolt = <1800000>;
 155                 regulator-max-microvolt = <1800000>;
 156                 regulator-always-on;
 157                 vin-supply = <&sw2_reg>;
 158         };
 159
 160         reg_audio_3v3: regulator-audio-3v3 {
 161                 compatible = "regulator-fixed";
 162                 regulator-name = "VCC3V3_AUDIO";
 163                 regulator-min-microvolt = <3300000>;
 164                 regulator-max-microvolt = <3300000>;
 165                 regulator-always-on;
 166         };
 167 };
 168
 169 &adc1 {
 170         vref-supply = <&reg_vref_1v8>;
 171         status = "okay";
 172 };
 173
 174 &adc2 {
 175         vref-supply = <&reg_vref_1v8>;
 176         status = "okay";
 177 };
 178
 179 &ecspi1 {
 180         pinctrl-names = "default";
 181         pinctrl-0 = <&pinctrl_ecspi1>;
 182         cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>,
 183                    <&gpio4 2 GPIO_ACTIVE_LOW>;
 184         status = "okay";
 185 };
 186
 187 &ecspi2 {
 188         pinctrl-names = "default";
 189         pinctrl-0 = <&pinctrl_ecspi2>;
 190         status = "okay";
 191 };
 192
 193 &fec1 {
 194         pinctrl-names = "default";
 195         pinctrl-0 = <&pinctrl_enet1>;
 196         phy-mode = "rgmii-id";
 197         phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
 198         phy-reset-duration = <1>;
 199         phy-reset-delay = <1>;
 200         phy-supply = <&reg_fec1_pwdn>;
 201         phy-handle = <&ethphy1_0>;
 202         fsl,magic-packet;
 203         status = "okay";
 204
 205         mdio {
 206                 #address-cells = <1>;
 207                 #size-cells = <0>;
 208
 209                 ethphy1_0: ethernet-phy@0 {
 210                         compatible = "ethernet-phy-ieee802.3-c22";
 211                         reg = <0>;
 212                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
 213                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
 214                         ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 215                         /* LED1: Link/Activity, LED2: Error */
 216                         ti,led-function = <0x0db0>;
 217                         /* Active low, LED1 and LED2 driven by phy */
 218                         ti,led-ctrl = <0x1001>;
 219                 };
 220         };
 221 };
 222
 223 &flexcan1 {
 224         pinctrl-names = "default";
 225         pinctrl-0 = <&pinctrl_flexcan1>;
 226         status = "okay";
 227 };
 228
 229 &flexcan2 {
 230         pinctrl-names = "default";
 231         pinctrl-0 = <&pinctrl_flexcan2>;
 232         status = "okay";
 233 };
 234
 235 &i2c1 {
 236         lm75: temperature-sensor@49 {
 237                 compatible = "national,lm75";
 238                 reg = <0x49>;
 239         };
 240 };
 241
 242 &i2c2 {
 243         clock-frequency = <100000>;
 244         pinctrl-names = "default";
 245         pinctrl-0 = <&pinctrl_i2c2>;
 246         status = "okay";
 247
 248         tlv320aic32x4: audio-codec@18 {
 249                 compatible = "ti,tlv320aic32x4";
 250                 reg = <0x18>;
 251                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 252                 clock-names = "mclk";
 253                 ldoin-supply = <&reg_audio_3v3>;
 254                 iov-supply = <&reg_audio_3v3>;
 255         };
 256
 257         pca9555: gpio-expander@20 {
 258                 compatible = "nxp,pca9555";
 259                 reg = <0x20>;
 260                 pinctrl-names = "default";
 261                 pinctrl-0 = <&pinctrl_pca9555>;
 262                 gpio-controller;
 263                 #gpio-cells = <2>;
 264                 interrupt-parent = <&gpio7>;
 265                 interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
 266                 interrupt-controller;
 267                 #interrupt-cells = <2>;
 268         };
 269 };
 270
 271 &i2c3 {
 272         clock-frequency = <100000>;
 273         pinctrl-names = "default";
 274         pinctrl-0 = <&pinctrl_i2c3>;
 275         status = "okay";
 276 };
 277
 278 &iomuxc {
 279         pinctrl-names = "default";
 280         pinctrl-0 = <&pinctrl_hog_mba7_1>;
 281
 282         pinctrl_ecspi1: ecspi1grp {
 283                 fsl,pins = <
 284                         MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO               0x7c
 285                         MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI               0x74
 286                         MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK               0x74
 287                         MX7D_PAD_UART1_RX_DATA__GPIO4_IO0               0x74
 288                         MX7D_PAD_UART1_TX_DATA__GPIO4_IO1               0x74
 289                         MX7D_PAD_UART2_RX_DATA__GPIO4_IO2               0x74
 290                 >;
 291         };
 292
 293         pinctrl_ecspi2: ecspi2grp {
 294                 fsl,pins = <
 295                         MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO               0x7c
 296                         MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI               0x74
 297                         MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK               0x74
 298                         MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0                 0x74
 299                 >;
 300         };
 301
 302         pinctrl_enet1: enet1grp {
 303                 fsl,pins = <
 304                         MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 0x02
 305                         MX7D_PAD_GPIO1_IO11__ENET1_MDC                  0x00
 306                         MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x71
 307                         MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x71
 308                         MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x71
 309                         MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x71
 310                         MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x71
 311                         MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71
 312                         MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x79
 313                         MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x79
 314                         MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x79
 315                         MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x79
 316                         MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x79
 317                         MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79
 318                         /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
 319                         MX7D_PAD_ENET1_COL__GPIO7_IO15          0x40000070
 320                         /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
 321                         MX7D_PAD_GPIO1_IO09__GPIO1_IO9          0x40000078
 322                 >;
 323         };
 324
 325         pinctrl_flexcan1: flexcan1grp {
 326                 fsl,pins = <
 327                         MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX        0x5a
 328                         MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX        0x52
 329                 >;
 330         };
 331
 332         pinctrl_flexcan2: flexcan2grp {
 333                 fsl,pins = <
 334                         MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x5a
 335                         MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x52
 336                 >;
 337         };
 338
 339         pinctrl_hog_mba7_1: hogmba71grp {
 340                 fsl,pins = <
 341                         /* Limitation: WDOG2_B / WDOG2_RESET not usable */
 342                         MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13       0x4000007c
 343                         MX7D_PAD_ENET1_CRS__GPIO7_IO14          0x40000074
 344                         /* #BOOT_EN */
 345                         MX7D_PAD_UART2_TX_DATA__GPIO4_IO3       0x40000010
 346                 >;
 347         };
 348
 349         pinctrl_i2c2: i2c2grp {
 350                 fsl,pins = <
 351                         MX7D_PAD_I2C2_SCL__I2C2_SCL             0x40000078
 352                         MX7D_PAD_I2C2_SDA__I2C2_SDA             0x40000078
 353                 >;
 354         };
 355
 356         pinctrl_i2c3: i2c3grp {
 357                 fsl,pins = <
 358                         MX7D_PAD_I2C3_SCL__I2C3_SCL             0x40000078
 359                         MX7D_PAD_I2C3_SDA__I2C3_SDA             0x40000078
 360                 >;
 361         };
 362
 363
 364         pinctrl_pca9555: pca95550grp {
 365                 fsl,pins = <
 366                         MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12       0x78
 367                 >;
 368         };
 369
 370         pinctrl_uart3: uart3grp {
 371                 fsl,pins = <
 372                         MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX    0x7e
 373                         MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX    0x76
 374                         MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS     0x76
 375                         MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS     0x7e
 376                 >;
 377         };
 378
 379         pinctrl_uart4: uart4grp {
 380                 fsl,pins = <
 381                         MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX     0x7e
 382                         MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX     0x76
 383                         MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS    0x76
 384                         MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS    0x7e
 385                 >;
 386         };
 387
 388         pinctrl_uart5: uart5grp {
 389                 fsl,pins = <
 390                         MX7D_PAD_I2C4_SCL__UART5_DCE_RX         0x7e
 391                         MX7D_PAD_I2C4_SDA__UART5_DCE_TX         0x76
 392                 >;
 393         };
 394
 395         pinctrl_uart6: uart6grp {
 396                 fsl,pins = <
 397                         MX7D_PAD_EPDC_DATA08__UART6_DCE_RX      0x7d
 398                         MX7D_PAD_EPDC_DATA09__UART6_DCE_TX      0x75
 399                         MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS     0x75
 400                         MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS     0x7d
 401                 >;
 402         };
 403
 404         pinctrl_uart7: uart7grp {
 405                 fsl,pins = <
 406                         MX7D_PAD_EPDC_DATA12__UART7_DCE_RX      0x7e
 407                         MX7D_PAD_EPDC_DATA13__UART7_DCE_TX      0x76
 408                         MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS     0x76
 409                         /* Limitation: RTS is not connected */
 410                         MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS     0x7e
 411                 >;
 412         };
 413
 414         pinctrl_usdhc1_gpio: usdhc1grp_gpio {
 415                 fsl,pins = <
 416                         /* WP */
 417                         MX7D_PAD_SD1_WP__GPIO5_IO1              0x7c
 418                         /* CD */
 419                         MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x7c
 420                         /* VSELECT */
 421                         MX7D_PAD_GPIO1_IO08__SD1_VSELECT        0x59
 422                 >;
 423         };
 424
 425         pinctrl_usdhc1: usdhc1grp {
 426                 fsl,pins = <
 427                         MX7D_PAD_SD1_CMD__SD1_CMD               0x5e
 428                         MX7D_PAD_SD1_CLK__SD1_CLK               0x57
 429                         MX7D_PAD_SD1_DATA0__SD1_DATA0           0x5e
 430                         MX7D_PAD_SD1_DATA1__SD1_DATA1           0x5e
 431                         MX7D_PAD_SD1_DATA2__SD1_DATA2           0x5e
 432                         MX7D_PAD_SD1_DATA3__SD1_DATA3           0x5e
 433                 >;
 434         };
 435
 436         pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
 437                 fsl,pins = <
 438                         MX7D_PAD_SD1_CMD__SD1_CMD               0x5a
 439                         MX7D_PAD_SD1_CLK__SD1_CLK               0x57
 440                         MX7D_PAD_SD1_DATA0__SD1_DATA0           0x5a
 441                         MX7D_PAD_SD1_DATA1__SD1_DATA1           0x5a
 442                         MX7D_PAD_SD1_DATA2__SD1_DATA2           0x5a
 443                         MX7D_PAD_SD1_DATA3__SD1_DATA3           0x5a
 444                 >;
 445         };
 446
 447         pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
 448                 fsl,pins = <
 449                         MX7D_PAD_SD1_CMD__SD1_CMD               0x5b
 450                         MX7D_PAD_SD1_CLK__SD1_CLK               0x57
 451                         MX7D_PAD_SD1_DATA0__SD1_DATA0           0x5b
 452                         MX7D_PAD_SD1_DATA1__SD1_DATA1           0x5b
 453                         MX7D_PAD_SD1_DATA2__SD1_DATA2           0x5b
 454                         MX7D_PAD_SD1_DATA3__SD1_DATA3           0x5b
 455                 >;
 456         };
 457 };
 458
 459 &iomuxc_lpsr {
 460         pinctrl_pwm1: pwm1grp {
 461                 fsl,pins = <
 462                         /* LCD_CONTRAST */
 463                         MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT      0x50
 464                 >;
 465         };
 466
 467         pinctrl_usbotg1: usbotg1grp {
 468                 fsl,pins = <
 469                         MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC   0x5c
 470                         MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5     0x59
 471                 >;
 472         };
 473 };
 474
 475 &pwm1 {
 476         pinctrl-names = "default";
 477         pinctrl-0 = <&pinctrl_pwm1>;
 478         status = "okay";
 479 };
 480
 481 &uart3 {
 482         pinctrl-names = "default";
 483         pinctrl-0 = <&pinctrl_uart3>;
 484         assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
 485         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 486         status = "okay";
 487 };
 488
 489 &uart4 {
 490         pinctrl-names = "default";
 491         pinctrl-0 = <&pinctrl_uart4>;
 492         assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
 493         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 494         status = "okay";
 495 };
 496
 497 &uart5 {
 498         pinctrl-names = "default";
 499         pinctrl-0 = <&pinctrl_uart5>;
 500         assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
 501         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 502         status = "okay";
 503 };
 504
 505 &uart6 {
 506         pinctrl-names = "default";
 507         pinctrl-0 = <&pinctrl_uart6>;
 508         assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
 509         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 510         status = "okay";
 511 };
 512
 513 &uart7 {
 514         pinctrl-names = "default";
 515         pinctrl-0 = <&pinctrl_uart7>;
 516         assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
 517         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 518         uart-has-rtscts;
 519         status = "okay";
 520 };
 521
 522 &usbh {
 523         status = "okay";
 524 };
 525
 526 &usbotg1 {
 527         pinctrl-names = "default";
 528         pinctrl-0 = <&pinctrl_usbotg1>;
 529         vbus-supply = <&reg_usb_otg1_vbus>;
 530         srp-disable;
 531         hnp-disable;
 532         adp-disable;
 533         dr_mode = "host";
 534         status = "okay";
 535 };
 536
 537 &usdhc1 {
 538         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 539         pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
 540         pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
 541         pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
 542         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 543         wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 544         vmmc-supply = <&reg_sd1_vmmc>;
 545         bus-width = <4>;
 546         no-1-8-v;
 547         status = "okay";
 548 };