arch/arm/boot/dts/imx6ull.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 //
   3 // Copyright 2016 Freescale Semiconductor, Inc.
   4
   5 #include "imx6ul.dtsi"
   6 #include "imx6ull-pinfunc.h"
   7 #include "imx6ull-pinfunc-snvs.h"
   8
   9 /* Delete UART8 in AIPS-1 (i.MX6UL specific) */
  10 /delete-node/ &uart8;
  11 /* Delete CAAM node in AIPS-2 (i.MX6UL specific) */
  12 /delete-node/ &crypto;
  13
  14 &cpu0 {
  15         clock-frequency = <900000000>;
  16         operating-points = <
  17                 /* kHz  uV */
  18                 900000  1275000
  19                 792000  1225000
  20                 528000  1175000
  21                 396000  1025000
  22                 198000  950000
  23         >;
  24         fsl,soc-operating-points = <
  25                 /* KHz  uV */
  26                 900000  1250000
  27                 792000  1175000
  28                 528000  1175000
  29                 396000  1175000
  30                 198000  1175000
  31         >;
  32 };
  33
  34 &ocotp {
  35         compatible = "fsl,imx6ull-ocotp", "syscon";
  36 };
  37
  38 &pxp {
  39         compatible = "fsl,imx6ull-pxp";
  40         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  41                      <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
  42 };
  43
  44 &usdhc1 {
  45         compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
  46 };
  47
  48 &usdhc2 {
  49         compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
  50 };
  51
  52 / {
  53         soc {
  54                 aips3: bus@2200000 {
  55                         compatible = "fsl,aips-bus", "simple-bus";
  56                         #address-cells = <1>;
  57                         #size-cells = <1>;
  58                         reg = <0x02200000 0x100000>;
  59                         ranges;
  60
  61                         dcp: crypto@2280000 {
  62                                 compatible = "fsl,imx6ull-dcp", "fsl,imx28-dcp";
  63                                 reg = <0x02280000 0x4000>;
  64                                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
  65                                              <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
  66                                              <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
  67                                 clocks = <&clks IMX6ULL_CLK_DCP_CLK>;
  68                                 clock-names = "dcp";
  69                         };
  70
  71                         rngb: rng@2284000 {
  72                                 compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb";
  73                                 reg = <0x02284000 0x4000>;
  74                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  75                                 clocks = <&clks IMX6UL_CLK_DUMMY>;
  76                         };
  77
  78                         iomuxc_snvs: iomuxc-snvs@2290000 {
  79                                 compatible = "fsl,imx6ull-iomuxc-snvs";
  80                                 reg = <0x02290000 0x4000>;
  81                         };
  82
  83                         uart8: serial@2288000 {
  84                                 compatible = "fsl,imx6ul-uart",
  85                                              "fsl,imx6q-uart";
  86                                 reg = <0x02288000 0x4000>;
  87                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
  88                                 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
  89                                          <&clks IMX6UL_CLK_UART8_SERIAL>;
  90                                 clock-names = "ipg", "per";
  91                                 status = "disabled";
  92                         };
  93                 };
  94         };
  95 };