arch/arm/boot/dts/imx6sll.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2017-2018 NXP.
   5  *
   6  */
   7
   8 #include <dt-bindings/clock/imx6sll-clock.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include "imx6sll-pinfunc.h"
  12
  13 / {
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         aliases {
  18                 gpio0 = &gpio1;
  19                 gpio1 = &gpio2;
  20                 gpio2 = &gpio3;
  21                 gpio3 = &gpio4;
  22                 gpio4 = &gpio5;
  23                 gpio5 = &gpio6;
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 mmc0 = &usdhc1;
  28                 mmc1 = &usdhc2;
  29                 mmc2 = &usdhc3;
  30                 serial0 = &uart1;
  31                 serial1 = &uart2;
  32                 serial2 = &uart3;
  33                 serial3 = &uart4;
  34                 serial4 = &uart5;
  35                 spi0 = &ecspi1;
  36                 spi1 = &ecspi2;
  37                 spi3 = &ecspi3;
  38                 spi4 = &ecspi4;
  39                 usbphy0 = &usbphy1;
  40                 usbphy1 = &usbphy2;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 cpu0: cpu@0 {
  48                         compatible = "arm,cortex-a9";
  49                         device_type = "cpu";
  50                         reg = <0>;
  51                         next-level-cache = <&L2>;
  52                         operating-points = <
  53                                 /* kHz    uV */
  54                                 996000  1275000
  55                                 792000  1175000
  56                                 396000  1075000
  57                                 198000  975000
  58                         >;
  59                         fsl,soc-operating-points = <
  60                                 /* ARM kHz      SOC-PU uV */
  61                                 996000          1175000
  62                                 792000          1175000
  63                                 396000          1175000
  64                                 198000          1175000
  65                         >;
  66                         clock-latency = <61036>; /* two CLK32 periods */
  67                         #cooling-cells = <2>;
  68                         clocks = <&clks IMX6SLL_CLK_ARM>,
  69                                  <&clks IMX6SLL_CLK_PLL2_PFD2>,
  70                                  <&clks IMX6SLL_CLK_STEP>,
  71                                  <&clks IMX6SLL_CLK_PLL1_SW>,
  72                                  <&clks IMX6SLL_CLK_PLL1_SYS>;
  73                         clock-names = "arm", "pll2_pfd2_396m", "step",
  74                                       "pll1_sw", "pll1_sys";
  75                         nvmem-cells = <&cpu_speed_grade>;
  76                         nvmem-cell-names = "speed_grade";
  77                 };
  78         };
  79
  80         ckil: clock-ckil {
  81                 compatible = "fixed-clock";
  82                 #clock-cells = <0>;
  83                 clock-frequency = <32768>;
  84                 clock-output-names = "ckil";
  85         };
  86
  87         osc: clock-osc-24m {
  88                 compatible = "fixed-clock";
  89                 #clock-cells = <0>;
  90                 clock-frequency = <24000000>;
  91                 clock-output-names = "osc";
  92         };
  93
  94         ipp_di0: clock-ipp-di0 {
  95                 compatible = "fixed-clock";
  96                 #clock-cells = <0>;
  97                 clock-frequency = <0>;
  98                 clock-output-names = "ipp_di0";
  99         };
 100
 101         ipp_di1: clock-ipp-di1 {
 102                 compatible = "fixed-clock";
 103                 #clock-cells = <0>;
 104                 clock-frequency = <0>;
 105                 clock-output-names = "ipp_di1";
 106         };
 107
 108         soc {
 109                 #address-cells = <1>;
 110                 #size-cells = <1>;
 111                 compatible = "simple-bus";
 112                 interrupt-parent = <&gpc>;
 113                 ranges;
 114
 115                 ocram: sram@900000 {
 116                         compatible = "mmio-sram";
 117                         reg = <0x00900000 0x20000>;
 118                 };
 119
 120                 intc: interrupt-controller@a01000 {
 121                         compatible = "arm,cortex-a9-gic";
 122                         #interrupt-cells = <3>;
 123                         interrupt-controller;
 124                         reg = <0x00a01000 0x1000>,
 125                               <0x00a00100 0x100>;
 126                         interrupt-parent = <&intc>;
 127                 };
 128
 129                 L2: cache-controller@a02000 {
 130                         compatible = "arm,pl310-cache";
 131                         reg = <0x00a02000 0x1000>;
 132                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 133                         cache-unified;
 134                         cache-level = <2>;
 135                         arm,tag-latency = <4 2 3>;
 136                         arm,data-latency = <4 2 3>;
 137                 };
 138
 139                 aips1: bus@2000000 {
 140                         compatible = "fsl,aips-bus", "simple-bus";
 141                         #address-cells = <1>;
 142                         #size-cells = <1>;
 143                         reg = <0x02000000 0x100000>;
 144                         ranges;
 145
 146                         spba: spba-bus@2000000 {
 147                                 compatible = "fsl,spba-bus", "simple-bus";
 148                                 #address-cells = <1>;
 149                                 #size-cells = <1>;
 150                                 reg = <0x02000000 0x40000>;
 151                                 ranges;
 152
 153                                 spdif: spdif@2004000 {
 154                                         compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif";
 155                                         reg = <0x02004000 0x4000>;
 156                                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 157                                         dmas = <&sdma 14 18 0>, <&sdma 15 18 0>;
 158                                         dma-names = "rx", "tx";
 159                                         clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>,
 160                                                  <&clks IMX6SLL_CLK_OSC>,
 161                                                  <&clks IMX6SLL_CLK_SPDIF>,
 162                                                  <&clks IMX6SLL_CLK_DUMMY>,
 163                                                  <&clks IMX6SLL_CLK_DUMMY>,
 164                                                  <&clks IMX6SLL_CLK_DUMMY>,
 165                                                  <&clks IMX6SLL_CLK_IPG>,
 166                                                  <&clks IMX6SLL_CLK_DUMMY>,
 167                                                  <&clks IMX6SLL_CLK_DUMMY>,
 168                                                  <&clks IMX6SLL_CLK_SPBA>;
 169                                         clock-names = "core", "rxtx0",
 170                                                       "rxtx1", "rxtx2",
 171                                                       "rxtx3", "rxtx4",
 172                                                       "rxtx5", "rxtx6",
 173                                                       "rxtx7", "dma";
 174                                         status = "disabled";
 175                                 };
 176
 177                                 ecspi1: spi@2008000 {
 178                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 179                                         reg = <0x02008000 0x4000>;
 180                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 181                                         dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 182                                         dma-names = "rx", "tx";
 183                                         clocks = <&clks IMX6SLL_CLK_ECSPI1>,
 184                                                  <&clks IMX6SLL_CLK_ECSPI1>;
 185                                         clock-names = "ipg", "per";
 186                                         status = "disabled";
 187                                 };
 188
 189                                 ecspi2: spi@200c000 {
 190                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 191                                         reg = <0x0200c000 0x4000>;
 192                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 193                                         dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 194                                         dma-names = "rx", "tx";
 195                                         clocks = <&clks IMX6SLL_CLK_ECSPI2>,
 196                                                  <&clks IMX6SLL_CLK_ECSPI2>;
 197                                         clock-names = "ipg", "per";
 198                                         status = "disabled";
 199                                 };
 200
 201                                 ecspi3: spi@2010000 {
 202                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 203                                         reg = <0x02010000 0x4000>;
 204                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 205                                         dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 206                                         dma-names = "rx", "tx";
 207                                         clocks = <&clks IMX6SLL_CLK_ECSPI3>,
 208                                                  <&clks IMX6SLL_CLK_ECSPI3>;
 209                                         clock-names = "ipg", "per";
 210                                         status = "disabled";
 211                                 };
 212
 213                                 ecspi4: spi@2014000 {
 214                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 215                                         reg = <0x02014000 0x4000>;
 216                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 217                                         dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 218                                         dma-names = "rx", "tx";
 219                                         clocks = <&clks IMX6SLL_CLK_ECSPI4>,
 220                                                  <&clks IMX6SLL_CLK_ECSPI4>;
 221                                         clock-names = "ipg", "per";
 222                                         status = "disabled";
 223                                 };
 224
 225                                 uart4: serial@2018000 {
 226                                         compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
 227                                                      "fsl,imx21-uart";
 228                                         reg = <0x02018000 0x4000>;
 229                                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 230                                         dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 231                                         dma-names = "rx", "tx";
 232                                         clocks = <&clks IMX6SLL_CLK_UART4_IPG>,
 233                                                  <&clks IMX6SLL_CLK_UART4_SERIAL>;
 234                                         clock-names = "ipg", "per";
 235                                         status = "disabled";
 236                                 };
 237
 238                                 uart1: serial@2020000 {
 239                                         compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
 240                                                      "fsl,imx21-uart";
 241                                         reg = <0x02020000 0x4000>;
 242                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 243                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 244                                         dma-names = "rx", "tx";
 245                                         clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
 246                                                  <&clks IMX6SLL_CLK_UART1_SERIAL>;
 247                                         clock-names = "ipg", "per";
 248                                         status = "disabled";
 249                                 };
 250
 251                                 uart2: serial@2024000 {
 252                                         compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
 253                                                      "fsl,imx21-uart";
 254                                         reg = <0x02024000 0x4000>;
 255                                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 256                                         dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 257                                         dma-names = "rx", "tx";
 258                                         clocks = <&clks IMX6SLL_CLK_UART2_IPG>,
 259                                                  <&clks IMX6SLL_CLK_UART2_SERIAL>;
 260                                         clock-names = "ipg", "per";
 261                                         status = "disabled";
 262                                 };
 263
 264                                 ssi1: ssi@2028000 {
 265                                         compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
 266                                         reg = <0x02028000 0x4000>;
 267                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 268                                         dmas = <&sdma 37 22 0>, <&sdma 38 22 0>;
 269                                         dma-names = "rx", "tx";
 270                                         fsl,fifo-depth = <15>;
 271                                         clocks = <&clks IMX6SLL_CLK_SSI1_IPG>,
 272                                                  <&clks IMX6SLL_CLK_SSI1>;
 273                                         clock-names = "ipg", "baud";
 274                                         status = "disabled";
 275                                 };
 276
 277                                 ssi2: ssi@202c000 {
 278                                         compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
 279                                         reg = <0x0202c000 0x4000>;
 280                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 281                                         dmas = <&sdma 41 22 0>, <&sdma 42 22 0>;
 282                                         dma-names = "rx", "tx";
 283                                         fsl,fifo-depth = <15>;
 284                                         clocks = <&clks IMX6SLL_CLK_SSI2_IPG>,
 285                                                  <&clks IMX6SLL_CLK_SSI2>;
 286                                         clock-names = "ipg", "baud";
 287                                         status = "disabled";
 288                                 };
 289
 290                                 ssi3: ssi@2030000 {
 291                                         compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
 292                                         reg = <0x02030000 0x4000>;
 293                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 294                                         dmas = <&sdma 45 22 0>, <&sdma 46 22 0>;
 295                                         dma-names = "rx", "tx";
 296                                         fsl,fifo-depth = <15>;
 297                                         clocks = <&clks IMX6SLL_CLK_SSI3_IPG>,
 298                                                  <&clks IMX6SLL_CLK_SSI3>;
 299                                         clock-names = "ipg", "baud";
 300                                         status = "disabled";
 301                                 };
 302
 303                                 uart3: serial@2034000 {
 304                                         compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
 305                                                      "fsl,imx21-uart";
 306                                         reg = <0x02034000 0x4000>;
 307                                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 308                                         dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 309                                         dma-name = "rx", "tx";
 310                                         clocks = <&clks IMX6SLL_CLK_UART3_IPG>,
 311                                                  <&clks IMX6SLL_CLK_UART3_SERIAL>;
 312                                         clock-names = "ipg", "per";
 313                                         status = "disabled";
 314                                 };
 315                         };
 316
 317                         pwm1: pwm@2080000 {
 318                                 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
 319                                 reg = <0x02080000 0x4000>;
 320                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 321                                 clocks = <&clks IMX6SLL_CLK_PWM1>,
 322                                          <&clks IMX6SLL_CLK_PWM1>;
 323                                 clock-names = "ipg", "per";
 324                                 #pwm-cells = <3>;
 325                         };
 326
 327                         pwm2: pwm@2084000 {
 328                                 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
 329                                 reg = <0x02084000 0x4000>;
 330                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 331                                 clocks = <&clks IMX6SLL_CLK_PWM2>,
 332                                          <&clks IMX6SLL_CLK_PWM2>;
 333                                 clock-names = "ipg", "per";
 334                                 #pwm-cells = <3>;
 335                         };
 336
 337                         pwm3: pwm@2088000 {
 338                                 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
 339                                 reg = <0x02088000 0x4000>;
 340                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 341                                 clocks = <&clks IMX6SLL_CLK_PWM3>,
 342                                          <&clks IMX6SLL_CLK_PWM3>;
 343                                 clock-names = "ipg", "per";
 344                                 #pwm-cells = <3>;
 345                         };
 346
 347                         pwm4: pwm@208c000 {
 348                                 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
 349                                 reg = <0x0208c000 0x4000>;
 350                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 351                                 clocks = <&clks IMX6SLL_CLK_PWM4>,
 352                                          <&clks IMX6SLL_CLK_PWM4>;
 353                                 clock-names = "ipg", "per";
 354                                 #pwm-cells = <3>;
 355                         };
 356
 357                         gpt1: timer@2098000 {
 358                                 compatible = "fsl,imx6sl-gpt";
 359                                 reg = <0x02098000 0x4000>;
 360                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 361                                 clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
 362                                          <&clks IMX6SLL_CLK_GPT_SERIAL>;
 363                                 clock-names = "ipg", "per";
 364                         };
 365
 366                         gpio1: gpio@209c000 {
 367                                 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 368                                 reg = <0x0209c000 0x4000>;
 369                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 370                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 371                                 clocks = <&clks IMX6SLL_CLK_GPIO1>;
 372                                 gpio-controller;
 373                                 #gpio-cells = <2>;
 374                                 interrupt-controller;
 375                                 #interrupt-cells = <2>;
 376                                 gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>;
 377                         };
 378
 379                         gpio2: gpio@20a0000 {
 380                                 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 381                                 reg = <0x020a0000 0x4000>;
 382                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 383                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 384                                 clocks = <&clks IMX6SLL_CLK_GPIO2>;
 385                                 gpio-controller;
 386                                 #gpio-cells = <2>;
 387                                 interrupt-controller;
 388                                 #interrupt-cells = <2>;
 389                                 gpio-ranges = <&iomuxc 0 50 32>;
 390                         };
 391
 392                         gpio3: gpio@20a4000 {
 393                                 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 394                                 reg = <0x020a4000 0x4000>;
 395                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 396                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 397                                 clocks = <&clks IMX6SLL_CLK_GPIO3>;
 398                                 gpio-controller;
 399                                 #gpio-cells = <2>;
 400                                 interrupt-controller;
 401                                 #interrupt-cells = <2>;
 402                                 gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>,
 403                                               <&iomuxc 16 101 2>, <&iomuxc 18 5 1>,
 404                                               <&iomuxc 21 6 11>;
 405                         };
 406
 407                         gpio4: gpio@20a8000 {
 408                                 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 409                                 reg = <0x020a8000 0x4000>;
 410                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 411                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 412                                 clocks = <&clks IMX6SLL_CLK_GPIO4>;
 413                                 gpio-controller;
 414                                 #gpio-cells = <2>;
 415                                 interrupt-controller;
 416                                 #interrupt-cells = <2>;
 417                                 gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>,
 418                                               <&iomuxc 16 151 1>, <&iomuxc 17 149 1>,
 419                                               <&iomuxc 18 146 1>, <&iomuxc 19 144 1>,
 420                                               <&iomuxc 20 142 1>, <&iomuxc 21 143 1>,
 421                                               <&iomuxc 22 150 1>, <&iomuxc 23 148 1>,
 422                                               <&iomuxc 24 147 1>, <&iomuxc 25 145 1>,
 423                                               <&iomuxc 26 152 1>, <&iomuxc 27 125 1>,
 424                                               <&iomuxc 28 131 1>, <&iomuxc 29 134 1>,
 425                                               <&iomuxc 30 129 1>, <&iomuxc 31 133 1>;
 426                         };
 427
 428                         gpio5: gpio@20ac000 {
 429                                 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 430                                 reg = <0x020ac000 0x4000>;
 431                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 432                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 433                                 clocks = <&clks IMX6SLL_CLK_GPIO5>;
 434                                 gpio-controller;
 435                                 #gpio-cells = <2>;
 436                                 interrupt-controller;
 437                                 #interrupt-cells = <2>;
 438                                 gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>,
 439                                               <&iomuxc 2 132 1>, <&iomuxc 3 130 1>,
 440                                               <&iomuxc 4 127 1>, <&iomuxc 5 126 1>,
 441                                               <&iomuxc 6 120 1>, <&iomuxc 7 123 1>,
 442                                               <&iomuxc 8 118 1>, <&iomuxc 9 122 1>,
 443                                               <&iomuxc 10 124 1>, <&iomuxc 11 117 1>,
 444                                               <&iomuxc 12 121 1>, <&iomuxc 13 119 1>,
 445                                               <&iomuxc 14 116 1>, <&iomuxc 15 115 1>,
 446                                               <&iomuxc 16 140 2>, <&iomuxc 18 136 1>,
 447                                               <&iomuxc 19 138 1>, <&iomuxc 20 139 1>,
 448                                               <&iomuxc 21 137 1>;
 449                         };
 450
 451                         gpio6: gpio@20b0000 {
 452                                 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
 453                                 reg = <0x020b0000 0x4000>;
 454                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 455                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 456                                 clocks = <&clks IMX6SLL_CLK_GPIO6>;
 457                                 gpio-controller;
 458                                 #gpio-cells = <2>;
 459                                 interrupt-controller;
 460                                 #interrupt-cells = <2>;
 461                         };
 462
 463                         kpp: keypad@20b8000 {
 464                                 compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp";
 465                                 reg = <0x020b8000 0x4000>;
 466                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 467                                 clocks = <&clks IMX6SLL_CLK_KPP>;
 468                                 status = "disabled";
 469                         };
 470
 471                         wdog1: watchdog@20bc000 {
 472                                 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
 473                                 reg = <0x020bc000 0x4000>;
 474                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 475                                 clocks = <&clks IMX6SLL_CLK_WDOG1>;
 476                         };
 477
 478                         wdog2: watchdog@20c0000 {
 479                                 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
 480                                 reg = <0x020c0000 0x4000>;
 481                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 482                                 clocks = <&clks IMX6SLL_CLK_WDOG2>;
 483                                 status = "disabled";
 484                         };
 485
 486                         clks: clock-controller@20c4000 {
 487                                 compatible = "fsl,imx6sll-ccm";
 488                                 reg = <0x020c4000 0x4000>;
 489                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 490                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 491                                 #clock-cells = <1>;
 492                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 493                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 494
 495                                 assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>;
 496                                 assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>;
 497                         };
 498
 499                         anatop: anatop@20c8000 {
 500                                 compatible = "fsl,imx6sll-anatop",
 501                                              "fsl,imx6q-anatop",
 502                                              "syscon", "simple-mfd";
 503                                 reg = <0x020c8000 0x4000>;
 504                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 505                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 506                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 507                                 #address-cells = <1>;
 508                                 #size-cells = <0>;
 509
 510                                 reg_3p0: regulator-3p0@20c8120 {
 511                                         compatible = "fsl,anatop-regulator";
 512                                         reg = <0x20c8120>;
 513                                         regulator-name = "vdd3p0";
 514                                         regulator-min-microvolt = <2625000>;
 515                                         regulator-max-microvolt = <3400000>;
 516                                         anatop-reg-offset = <0x120>;
 517                                         anatop-vol-bit-shift = <8>;
 518                                         anatop-vol-bit-width = <5>;
 519                                         anatop-min-bit-val = <0>;
 520                                         anatop-min-voltage = <2625000>;
 521                                         anatop-max-voltage = <3400000>;
 522                                         anatop-enable-bit = <0>;
 523                                 };
 524
 525                                 tempmon: temperature-sensor {
 526                                         compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
 527                                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 528                                         interrupt-parent = <&gpc>;
 529                                         fsl,tempmon = <&anatop>;
 530                                         nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
 531                                         nvmem-cell-names = "calib", "temp_grade";
 532                                         clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
 533                                 };
 534                         };
 535
 536                         usbphy1: usb-phy@20c9000 {
 537                                 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
 538                                                 "fsl,imx23-usbphy";
 539                                 reg = <0x020c9000 0x1000>;
 540                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 541                                 clocks = <&clks IMX6SLL_CLK_USBPHY1>;
 542                                 phy-3p0-supply = <&reg_3p0>;
 543                                 fsl,anatop = <&anatop>;
 544                         };
 545
 546                         usbphy2: usb-phy@20ca000 {
 547                                 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
 548                                                 "fsl,imx23-usbphy";
 549                                 reg = <0x020ca000 0x1000>;
 550                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 551                                 clocks = <&clks IMX6SLL_CLK_USBPHY2>;
 552                                 phy-reg_3p0-supply = <&reg_3p0>;
 553                                 fsl,anatop = <&anatop>;
 554                         };
 555
 556                         snvs: snvs@20cc000 {
 557                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 558                                 reg = <0x020cc000 0x4000>;
 559
 560                                 snvs_rtc: snvs-rtc-lp {
 561                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 562                                         regmap = <&snvs>;
 563                                         offset = <0x34>;
 564                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 565                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 566                                 };
 567
 568                                 snvs_poweroff: snvs-poweroff {
 569                                         compatible = "syscon-poweroff";
 570                                         regmap = <&snvs>;
 571                                         offset = <0x38>;
 572                                         mask = <0x61>;
 573                                         status = "disabled";
 574                                 };
 575
 576                                 snvs_pwrkey: snvs-powerkey {
 577                                         compatible = "fsl,sec-v4.0-pwrkey";
 578                                         regmap = <&snvs>;
 579                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 580                                         linux,keycode = <KEY_POWER>;
 581                                         wakeup-source;
 582                                         status = "disabled";
 583                                 };
 584                         };
 585
 586                         src: reset-controller@20d8000 {
 587                                 compatible = "fsl,imx6sll-src", "fsl,imx51-src";
 588                                 reg = <0x020d8000 0x4000>;
 589                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 590                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 591                                 #reset-cells = <1>;
 592                         };
 593
 594                         gpc: interrupt-controller@20dc000 {
 595                                 compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc";
 596                                 reg = <0x020dc000 0x4000>;
 597                                 interrupt-controller;
 598                                 #interrupt-cells = <3>;
 599                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 600                                 interrupt-parent = <&intc>;
 601                         };
 602
 603                         iomuxc: pinctrl@20e0000 {
 604                                 compatible = "fsl,imx6sll-iomuxc";
 605                                 reg = <0x020e0000 0x4000>;
 606                         };
 607
 608                         gpr: iomuxc-gpr@20e4000 {
 609                                 compatible = "fsl,imx6sll-iomuxc-gpr",
 610                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 611                                 reg = <0x020e4000 0x4000>;
 612                         };
 613
 614                         csi: csi@20e8000 {
 615                                 compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
 616                                 reg = <0x020e8000 0x4000>;
 617                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 618                                 clocks = <&clks IMX6SLL_CLK_DUMMY>,
 619                                          <&clks IMX6SLL_CLK_CSI>,
 620                                          <&clks IMX6SLL_CLK_DUMMY>;
 621                                 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
 622                                 status = "disabled";
 623                         };
 624
 625                         sdma: dma-controller@20ec000 {
 626                                 compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma";
 627                                 reg = <0x020ec000 0x4000>;
 628                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 629                                 clocks = <&clks IMX6SLL_CLK_IPG>,
 630                                          <&clks IMX6SLL_CLK_SDMA>;
 631                                 clock-names = "ipg", "ahb";
 632                                 #dma-cells = <3>;
 633                                 iram = <&ocram>;
 634                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 635                         };
 636
 637                         pxp: pxp@20f0000 {
 638                                 compatible = "fsl,imx6sll-pxp", "fsl,imx6ull-pxp";
 639                                 reg = <0x20f0000 0x4000>;
 640                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 641                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 642                                 clocks = <&clks IMX6SLL_CLK_PXP>;
 643                                 clock-names = "axi";
 644                         };
 645
 646                         lcdif: lcd-controller@20f8000 {
 647                                 compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
 648                                 reg = <0x020f8000 0x4000>;
 649                                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 650                                 clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
 651                                          <&clks IMX6SLL_CLK_LCDIF_APB>,
 652                                          <&clks IMX6SLL_CLK_DUMMY>;
 653                                 clock-names = "pix", "axi", "disp_axi";
 654                                 status = "disabled";
 655                         };
 656
 657                         dcp: crypto@20fc000 {
 658                                 compatible = "fsl,imx28-dcp";
 659                                 reg = <0x020fc000 0x4000>;
 660                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 661                                              <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 662                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 663                                 clocks = <&clks IMX6SLL_CLK_DCP>;
 664                                 clock-names = "dcp";
 665                         };
 666                 };
 667
 668                 aips2: bus@2100000 {
 669                         compatible = "fsl,aips-bus", "simple-bus";
 670                         #address-cells = <1>;
 671                         #size-cells = <1>;
 672                         reg = <0x02100000 0x100000>;
 673                         ranges;
 674
 675                         usbotg1: usb@2184000 {
 676                                 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
 677                                                 "fsl,imx27-usb";
 678                                 reg = <0x02184000 0x200>;
 679                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 680                                 clocks = <&clks IMX6SLL_CLK_USBOH3>;
 681                                 fsl,usbphy = <&usbphy1>;
 682                                 fsl,usbmisc = <&usbmisc 0>;
 683                                 fsl,anatop = <&anatop>;
 684                                 ahb-burst-config = <0x0>;
 685                                 tx-burst-size-dword = <0x10>;
 686                                 rx-burst-size-dword = <0x10>;
 687                                 status = "disabled";
 688                         };
 689
 690                         usbotg2: usb@2184200 {
 691                                 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
 692                                                 "fsl,imx27-usb";
 693                                 reg = <0x02184200 0x200>;
 694                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 695                                 clocks = <&clks IMX6SLL_CLK_USBOH3>;
 696                                 fsl,usbphy = <&usbphy2>;
 697                                 fsl,usbmisc = <&usbmisc 1>;
 698                                 ahb-burst-config = <0x0>;
 699                                 tx-burst-size-dword = <0x10>;
 700                                 rx-burst-size-dword = <0x10>;
 701                                 status = "disabled";
 702                         };
 703
 704                         usbmisc: usbmisc@2184800 {
 705                                 #index-cells = <1>;
 706                                 compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc",
 707                                                 "fsl,imx6q-usbmisc";
 708                                 reg = <0x02184800 0x200>;
 709                         };
 710
 711                         usdhc1: mmc@2190000 {
 712                                 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
 713                                 reg = <0x02190000 0x4000>;
 714                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 715                                 clocks = <&clks IMX6SLL_CLK_USDHC1>,
 716                                          <&clks IMX6SLL_CLK_USDHC1>,
 717                                          <&clks IMX6SLL_CLK_USDHC1>;
 718                                 clock-names = "ipg", "ahb", "per";
 719                                 bus-width = <4>;
 720                                 fsl,tuning-step = <2>;
 721                                 fsl,tuning-start-tap = <20>;
 722                                 status = "disabled";
 723                         };
 724
 725                         usdhc2: mmc@2194000 {
 726                                 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
 727                                 reg = <0x02194000 0x4000>;
 728                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 729                                 clocks = <&clks IMX6SLL_CLK_USDHC2>,
 730                                          <&clks IMX6SLL_CLK_USDHC2>,
 731                                          <&clks IMX6SLL_CLK_USDHC2>;
 732                                 clock-names = "ipg", "ahb", "per";
 733                                 bus-width = <4>;
 734                                 fsl,tuning-step = <2>;
 735                                 fsl,tuning-start-tap = <20>;
 736                                 status = "disabled";
 737                         };
 738
 739                         usdhc3: mmc@2198000 {
 740                                 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
 741                                 reg = <0x02198000 0x4000>;
 742                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 743                                 clocks = <&clks IMX6SLL_CLK_USDHC3>,
 744                                          <&clks IMX6SLL_CLK_USDHC3>,
 745                                          <&clks IMX6SLL_CLK_USDHC3>;
 746                                 clock-names = "ipg", "ahb", "per";
 747                                 bus-width = <4>;
 748                                 fsl,tuning-step = <2>;
 749                                 fsl,tuning-start-tap = <20>;
 750                                 status = "disabled";
 751                         };
 752
 753                         i2c1: i2c@21a0000 {
 754                                 #address-cells = <1>;
 755                                 #size-cells = <0>;
 756                                 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
 757                                 reg = <0x021a0000 0x4000>;
 758                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 759                                 clocks = <&clks IMX6SLL_CLK_I2C1>;
 760                                 status = "disabled";
 761                         };
 762
 763                         i2c2: i2c@21a4000 {
 764                                 #address-cells = <1>;
 765                                 #size-cells = <0>;
 766                                 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
 767                                 reg = <0x021a4000 0x4000>;
 768                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 769                                 clocks = <&clks IMX6SLL_CLK_I2C2>;
 770                                 status = "disabled";
 771                         };
 772
 773                         i2c3: i2c@21a8000 {
 774                                 #address-cells = <1>;
 775                                 #size-cells = <0>;
 776                                 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
 777                                 reg = <0x021a8000 0x4000>;
 778                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 779                                 clocks = <&clks IMX6SLL_CLK_I2C3>;
 780                                 status = "disabled";
 781                         };
 782
 783                         mmdc: memory-controller@21b0000 {
 784                                 compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
 785                                 reg = <0x021b0000 0x4000>;
 786                                 clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
 787                         };
 788
 789                         rngb: rng@21b4000 {
 790                                 compatible = "fsl,imx6sll-rngb", "fsl,imx25-rngb";
 791                                 reg = <0x021b4000 0x4000>;
 792                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 793                                 clocks = <&clks IMX6SLL_CLK_DUMMY>;
 794                         };
 795
 796                         ocotp: efuse@21bc000 {
 797                                 #address-cells = <1>;
 798                                 #size-cells = <1>;
 799                                 compatible = "fsl,imx6sll-ocotp", "syscon";
 800                                 reg = <0x021bc000 0x4000>;
 801                                 clocks = <&clks IMX6SLL_CLK_OCOTP>;
 802
 803                                 cpu_speed_grade: speed-grade@10 {
 804                                         reg = <0x10 4>;
 805                                 };
 806
 807                                 tempmon_calib: calib@38 {
 808                                         reg = <0x38 4>;
 809                                 };
 810
 811                                 tempmon_temp_grade: temp-grade@20 {
 812                                         reg = <0x20 4>;
 813                                 };
 814                         };
 815
 816                         audmux: audmux@21d8000 {
 817                                 compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux";
 818                                 reg = <0x021d8000 0x4000>;
 819                                 status = "disabled";
 820                         };
 821
 822                         uart5: serial@21f4000 {
 823                                 compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart",
 824                                              "fsl,imx21-uart";
 825                                 reg = <0x021f4000 0x4000>;
 826                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 827                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 828                                 dma-names = "rx", "tx";
 829                                 clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
 830                                          <&clks IMX6SLL_CLK_UART5_SERIAL>;
 831                                 clock-names = "ipg", "per";
 832                                 status = "disabled";
 833                         };
 834                 };
 835         };
 836 };