arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2018 PHYTEC Messtechnik GmbH
   4  * Author: Christian Hemp <c.hemp@phytec.de>
   5  */
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/regulator/dlg,da9063-regulator.h>
   9
  10 / {
  11         aliases {
  12                 rtc1 = &da9062_rtc;
  13                 rtc2 = &snvs_rtc;
  14         };
  15
  16         /*
  17          * Set the minimum memory size here and
  18          * let the bootloader set the real size.
  19          */
  20         memory@10000000 {
  21                 device_type = "memory";
  22                 reg = <0x10000000 0x8000000>;
  23         };
  24
  25         gpio_leds_som: somleds {
  26                 compatible = "gpio-leds";
  27                 pinctrl-names = "default";
  28                 pinctrl-0 = <&pinctrl_gpioleds_som>;
  29
  30                 som-led-green {
  31                         label = "phycore:green";
  32                         gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
  33                         linux,default-trigger = "heartbeat";
  34                 };
  35         };
  36 };
  37
  38 &ecspi1 {
  39         pinctrl-names = "default";
  40         pinctrl-0 = <&pinctrl_ecspi1>;
  41         cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
  42         status = "okay";
  43
  44         m25p80: flash@0 {
  45                 compatible = "jedec,spi-nor";
  46                 spi-max-frequency = <20000000>;
  47                 reg = <0>;
  48                 status = "disabled";
  49         };
  50 };
  51
  52 &fec {
  53         pinctrl-names = "default";
  54         pinctrl-0 = <&pinctrl_enet>;
  55         phy-handle = <&ethphy>;
  56         phy-mode = "rgmii";
  57         phy-supply = <&vdd_eth_io>;
  58         phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
  59         status = "disabled";
  60
  61         mdio {
  62                 #address-cells = <1>;
  63                 #size-cells = <0>;
  64
  65                 ethphy: ethernet-phy@3 {
  66                         reg = <3>;
  67                         txc-skew-ps = <1680>;
  68                         rxc-skew-ps = <1860>;
  69                 };
  70         };
  71 };
  72
  73 &gpmi {
  74         pinctrl-names = "default";
  75         pinctrl-0 = <&pinctrl_gpmi_nand>;
  76         nand-on-flash-bbt;
  77         status = "disabled";
  78 };
  79
  80 &i2c3 {
  81         pinctrl-names = "default";
  82         pinctrl-0 = <&pinctrl_i2c3>;
  83         clock-frequency = <400000>;
  84         status = "okay";
  85
  86         eeprom@50 {
  87                 compatible = "atmel,24c32";
  88                 reg = <0x50>;
  89         };
  90
  91         pmic@58 {
  92                 compatible = "dlg,da9062";
  93                 pinctrl-names = "default";
  94                 pinctrl-0 = <&pinctrl_pmic>;
  95                 reg = <0x58>;
  96                 interrupt-parent = <&gpio1>;
  97                 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
  98                 interrupt-controller;
  99
 100                 da9062_rtc: rtc {
 101                         compatible = "dlg,da9062-rtc";
 102                 };
 103
 104                 da9062_onkey: onkey {
 105                         compatible = "dlg,da9062-onkey";
 106                 };
 107
 108                 watchdog {
 109                         compatible = "dlg,da9062-watchdog";
 110                 };
 111
 112                 regulators {
 113                         vdd_arm: buck1 {
 114                                 regulator-name = "vdd_arm";
 115                                 regulator-min-microvolt = <925000>;
 116                                 regulator-max-microvolt = <1380000>;
 117                                 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
 118                                 regulator-always-on;
 119                         };
 120
 121                         vdd_soc: buck2 {
 122                                 regulator-name = "vdd_soc";
 123                                 regulator-min-microvolt = <1150000>;
 124                                 regulator-max-microvolt = <1380000>;
 125                                 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
 126                                 regulator-always-on;
 127                         };
 128
 129                         vdd_ddr3_1p5: buck3 {
 130                                 regulator-name = "vdd_ddr3";
 131                                 regulator-min-microvolt = <1500000>;
 132                                 regulator-max-microvolt = <1500000>;
 133                                 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
 134                                 regulator-always-on;
 135                         };
 136
 137                         vdd_eth_1p2: buck4 {
 138                                 regulator-name = "vdd_eth";
 139                                 regulator-min-microvolt = <1200000>;
 140                                 regulator-max-microvolt = <1200000>;
 141                                 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
 142                                 regulator-always-on;
 143                         };
 144
 145                         vdd_snvs: ldo1 {
 146                                 regulator-name = "vdd_snvs";
 147                                 regulator-min-microvolt = <3000000>;
 148                                 regulator-max-microvolt = <3000000>;
 149                                 regulator-always-on;
 150                         };
 151
 152                         vdd_high: ldo2 {
 153                                 regulator-name = "vdd_high";
 154                                 regulator-min-microvolt = <3000000>;
 155                                 regulator-max-microvolt = <3000000>;
 156                                 regulator-always-on;
 157                         };
 158
 159                         vdd_eth_io: ldo3 {
 160                                 regulator-name = "vdd_eth_io";
 161                                 regulator-min-microvolt = <2500000>;
 162                                 regulator-max-microvolt = <2500000>;
 163                         };
 164
 165                         vdd_emmc_1p8: ldo4 {
 166                                 regulator-name = "vdd_emmc";
 167                                 regulator-min-microvolt = <1800000>;
 168                                 regulator-max-microvolt = <1800000>;
 169                         };
 170                 };
 171         };
 172 };
 173
 174 &reg_arm {
 175         vin-supply = <&vdd_arm>;
 176 };
 177
 178 &reg_pu {
 179         vin-supply = <&vdd_soc>;
 180 };
 181
 182 &reg_soc {
 183         vin-supply = <&vdd_soc>;
 184 };
 185
 186 &snvs_poweroff {
 187         status = "okay";
 188 };
 189
 190 &usdhc4 {
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&pinctrl_usdhc4>;
 193         bus-width = <8>;
 194         non-removable;
 195         status = "disabled";
 196 };
 197
 198 &iomuxc {
 199         pinctrl_enet: enetgrp {
 200                 fsl,pins = <
 201                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 202                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 203                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 204                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 205                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 206                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 207                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 208                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 209                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 210                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 211                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 212                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 213                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 214                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 215                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 216                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 217                         MX6QDL_PAD_SD2_DAT1__GPIO1_IO14         0x1b0b0
 218                 >;
 219         };
 220
 221         pinctrl_gpioleds_som: gpioledssomgrp {
 222                 fsl,pins = <
 223                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0
 224                 >;
 225         };
 226
 227         pinctrl_gpmi_nand: gpminandgrp {
 228                 fsl,pins = <
 229                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 230                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 231                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 232                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 233                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 234                         MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 235                         MX6QDL_PAD_NANDF_CS2__NAND_CE2_B        0xb0b1
 236                         MX6QDL_PAD_NANDF_CS3__NAND_CE3_B        0xb0b1
 237                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 238                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 239                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 240                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 241                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 242                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 243                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 244                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 245                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 246                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 247                         MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 248                 >;
 249         };
 250
 251         pinctrl_i2c3: i2c3grp {
 252                 fsl,pins = <
 253                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 254                         MX6QDL_PAD_GPIO_5__I2C3_SCL             0x4001b8b1
 255                 >;
 256         };
 257
 258         pinctrl_ecspi1: ecspi1grp {
 259                 fsl,pins = <
 260                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 261                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 262                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 263                         MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x1b0b0
 264                 >;
 265         };
 266
 267         pinctrl_pmic: pmicgrp {
 268                 fsl,pins = <
 269                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b0
 270                 >;
 271         };
 272
 273         pinctrl_usdhc4: usdhc4grp {
 274                 fsl,pins = <
 275                         MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
 276                         MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
 277                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
 278                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
 279                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
 280                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
 281                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
 282                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
 283                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
 284                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
 285                 >;
 286         };
 287 };