arch/arm/boot/dts/imx6qdl-gw5907.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2019 Gateworks Corporation
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/linux-event-codes.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9
  10 / {
  11         /* these are used by bootloader for disabling nodes */
  12         aliases {
  13                 led0 = &led0;
  14                 led1 = &led1;
  15                 nand = &gpmi;
  16                 usb0 = &usbh1;
  17                 usb1 = &usbotg;
  18         };
  19
  20         chosen {
  21                 stdout-path = &uart2;
  22         };
  23
  24         gpio-keys {
  25                 compatible = "gpio-keys";
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 user-pb {
  30                         label = "user_pb";
  31                         gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  32                         linux,code = <BTN_0>;
  33                 };
  34
  35                 user-pb1x {
  36                         label = "user_pb1x";
  37                         linux,code = <BTN_1>;
  38                         interrupt-parent = <&gsc>;
  39                         interrupts = <0>;
  40                 };
  41
  42                 key-erased {
  43                         label = "key-erased";
  44                         linux,code = <BTN_2>;
  45                         interrupt-parent = <&gsc>;
  46                         interrupts = <1>;
  47                 };
  48
  49                 eeprom-wp {
  50                         label = "eeprom_wp";
  51                         linux,code = <BTN_3>;
  52                         interrupt-parent = <&gsc>;
  53                         interrupts = <2>;
  54                 };
  55
  56                 tamper {
  57                         label = "tamper";
  58                         linux,code = <BTN_4>;
  59                         interrupt-parent = <&gsc>;
  60                         interrupts = <5>;
  61                 };
  62
  63                 switch-hold {
  64                         label = "switch_hold";
  65                         linux,code = <BTN_5>;
  66                         interrupt-parent = <&gsc>;
  67                         interrupts = <7>;
  68                 };
  69         };
  70
  71         leds {
  72                 compatible = "gpio-leds";
  73                 pinctrl-names = "default";
  74                 pinctrl-0 = <&pinctrl_gpio_leds>;
  75
  76                 led0: user1 {
  77                         label = "user1";
  78                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  79                         default-state = "on";
  80                         linux,default-trigger = "heartbeat";
  81                 };
  82
  83                 led1: user2 {
  84                         label = "user2";
  85                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  86                         default-state = "off";
  87                 };
  88         };
  89
  90         memory@10000000 {
  91                 device_type = "memory";
  92                 reg = <0x10000000 0x20000000>;
  93         };
  94
  95         pps {
  96                 compatible = "pps-gpio";
  97                 pinctrl-names = "default";
  98                 pinctrl-0 = <&pinctrl_pps>;
  99                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 100                 status = "okay";
 101         };
 102
 103         reg_3p3v: regulator-3p3v {
 104                 compatible = "regulator-fixed";
 105                 regulator-name = "3P3V";
 106                 regulator-min-microvolt = <3300000>;
 107                 regulator-max-microvolt = <3300000>;
 108                 regulator-always-on;
 109         };
 110
 111         reg_5p0v: regulator-5p0v {
 112                 compatible = "regulator-fixed";
 113                 regulator-name = "5P0V";
 114                 regulator-min-microvolt = <5000000>;
 115                 regulator-max-microvolt = <5000000>;
 116                 regulator-always-on;
 117         };
 118
 119         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 120                 compatible = "regulator-fixed";
 121                 regulator-name = "usb_otg_vbus";
 122                 regulator-min-microvolt = <5000000>;
 123                 regulator-max-microvolt = <5000000>;
 124                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 125                 enable-active-high;
 126         };
 127 };
 128
 129 &fec {
 130         pinctrl-names = "default";
 131         pinctrl-0 = <&pinctrl_enet>;
 132         phy-mode = "rgmii-id";
 133         phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 134         status = "okay";
 135 };
 136
 137 &gpmi {
 138         pinctrl-names = "default";
 139         pinctrl-0 = <&pinctrl_gpmi_nand>;
 140         status = "okay";
 141 };
 142
 143 &hdmi {
 144         ddc-i2c-bus = <&i2c3>;
 145         status = "okay";
 146 };
 147
 148 &i2c1 {
 149         clock-frequency = <100000>;
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&pinctrl_i2c1>;
 152         status = "okay";
 153
 154         gsc: gsc@20 {
 155                 compatible = "gw,gsc";
 156                 reg = <0x20>;
 157                 interrupt-parent = <&gpio1>;
 158                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 159                 interrupt-controller;
 160                 #interrupt-cells = <1>;
 161                 #size-cells = <0>;
 162
 163                 adc {
 164                         compatible = "gw,gsc-adc";
 165                         #address-cells = <1>;
 166                         #size-cells = <0>;
 167
 168                         channel@0 {
 169                                 gw,mode = <0>;
 170                                 reg = <0x00>;
 171                                 label = "temp";
 172                         };
 173
 174                         channel@2 {
 175                                 gw,mode = <1>;
 176                                 reg = <0x02>;
 177                                 label = "vdd_vin";
 178                         };
 179
 180                         channel@5 {
 181                                 gw,mode = <1>;
 182                                 reg = <0x05>;
 183                                 label = "vdd_3p3";
 184                         };
 185
 186                         channel@8 {
 187                                 gw,mode = <1>;
 188                                 reg = <0x08>;
 189                                 label = "vdd_bat";
 190                         };
 191
 192                         channel@b {
 193                                 gw,mode = <1>;
 194                                 reg = <0x0b>;
 195                                 label = "vdd_5p0";
 196                         };
 197
 198                         channel@e {
 199                                 gw,mode = <1>;
 200                                 reg = <0xe>;
 201                                 label = "vdd_arm";
 202                         };
 203
 204                         channel@11 {
 205                                 gw,mode = <1>;
 206                                 reg = <0x11>;
 207                                 label = "vdd_soc";
 208                         };
 209
 210                         channel@14 {
 211                                 gw,mode = <1>;
 212                                 reg = <0x14>;
 213                                 label = "vdd_3p0";
 214                         };
 215
 216                         channel@17 {
 217                                 gw,mode = <1>;
 218                                 reg = <0x17>;
 219                                 label = "vdd_1p5";
 220                         };
 221
 222                         channel@1d {
 223                                 gw,mode = <1>;
 224                                 reg = <0x1d>;
 225                                 label = "vdd_1p8";
 226                         };
 227
 228                         channel@20 {
 229                                 gw,mode = <1>;
 230                                 reg = <0x20>;
 231                                 label = "vdd_an1";
 232                         };
 233
 234                         channel@23 {
 235                                 gw,mode = <1>;
 236                                 reg = <0x23>;
 237                                 label = "vdd_2p5";
 238                         };
 239                 };
 240         };
 241
 242         gsc_gpio: gpio@23 {
 243                 compatible = "nxp,pca9555";
 244                 reg = <0x23>;
 245                 gpio-controller;
 246                 #gpio-cells = <2>;
 247                 interrupt-parent = <&gsc>;
 248                 interrupts = <4>;
 249         };
 250
 251         eeprom@50 {
 252                 compatible = "atmel,24c02";
 253                 reg = <0x50>;
 254                 pagesize = <16>;
 255         };
 256
 257         eeprom@51 {
 258                 compatible = "atmel,24c02";
 259                 reg = <0x51>;
 260                 pagesize = <16>;
 261         };
 262
 263         eeprom@52 {
 264                 compatible = "atmel,24c02";
 265                 reg = <0x52>;
 266                 pagesize = <16>;
 267         };
 268
 269         eeprom@53 {
 270                 compatible = "atmel,24c02";
 271                 reg = <0x53>;
 272                 pagesize = <16>;
 273         };
 274
 275         ds1672@68 {
 276                 compatible = "dallas,ds1672";
 277                 reg = <0x68>;
 278         };
 279 };
 280
 281 &i2c2 {
 282         clock-frequency = <100000>;
 283         pinctrl-names = "default";
 284         pinctrl-0 = <&pinctrl_i2c2>;
 285         status = "okay";
 286 };
 287
 288 &i2c3 {
 289         clock-frequency = <100000>;
 290         pinctrl-names = "default";
 291         pinctrl-0 = <&pinctrl_i2c3>;
 292         status = "okay";
 293
 294         gpio@20 {
 295                 compatible = "nxp,pca9555";
 296                 reg = <0x20>;
 297                 gpio-controller;
 298                 #gpio-cells = <2>;
 299         };
 300
 301         adc@48 {
 302                 compatible = "ti,ads1015";
 303                 reg = <0x48>;
 304                 #address-cells = <1>;
 305                 #size-cells = <0>;
 306
 307                 channel@4 {
 308                         reg = <4>;
 309                         ti,gain = <0>;
 310                         ti,datarate = <5>;
 311                 };
 312
 313                 channel@5 {
 314                         reg = <5>;
 315                         ti,gain = <0>;
 316                         ti,datarate = <5>;
 317                 };
 318
 319                 channel@6 {
 320                         reg = <6>;
 321                         ti,gain = <0>;
 322                         ti,datarate = <5>;
 323                 };
 324         };
 325 };
 326
 327 &pcie {
 328         pinctrl-names = "default";
 329         pinctrl-0 = <&pinctrl_pcie>;
 330         reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 331         status = "okay";
 332 };
 333
 334 &pwm2 {
 335         pinctrl-names = "default";
 336         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 337         status = "disabled";
 338 };
 339
 340 &pwm3 {
 341         pinctrl-names = "default";
 342         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 343         status = "disabled";
 344 };
 345
 346 &pwm4 {
 347         pinctrl-names = "default";
 348         pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
 349         status = "disabled";
 350 };
 351
 352 &uart1 {
 353         pinctrl-names = "default";
 354         pinctrl-0 = <&pinctrl_uart1>;
 355         status = "okay";
 356 };
 357
 358 &uart2 {
 359         pinctrl-names = "default";
 360         pinctrl-0 = <&pinctrl_uart2>;
 361         status = "okay";
 362 };
 363
 364 &uart3 {
 365         pinctrl-names = "default";
 366         pinctrl-0 = <&pinctrl_uart3>;
 367         status = "okay";
 368 };
 369
 370 &uart5 {
 371         pinctrl-names = "default";
 372         pinctrl-0 = <&pinctrl_uart5>;
 373         status = "okay";
 374 };
 375
 376 &usbotg {
 377         vbus-supply = <&reg_usb_otg_vbus>;
 378         pinctrl-names = "default";
 379         pinctrl-0 = <&pinctrl_usbotg>;
 380         disable-over-current;
 381         status = "okay";
 382 };
 383
 384 &usbh1 {
 385         status = "okay";
 386 };
 387
 388 &wdog1 {
 389         pinctrl-names = "default";
 390         pinctrl-0 = <&pinctrl_wdog>;
 391         fsl,ext-reset-output;
 392 };
 393
 394 &iomuxc {
 395         pinctrl_enet: enetgrp {
 396                 fsl,pins = <
 397                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 398                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 399                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 400                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 401                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 402                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 403                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 404                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 405                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 406                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 407                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 408                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 409                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 410                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 411                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 412                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 413                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
 414                 >;
 415         };
 416
 417         pinctrl_gpio_leds: gpioledsgrp {
 418                 fsl,pins = <
 419                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 420                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 421                 >;
 422         };
 423
 424         pinctrl_gpmi_nand: gpminandgrp {
 425                 fsl,pins = <
 426                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 427                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 428                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 429                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 430                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 431                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 432                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 433                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 434                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 435                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 436                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 437                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 438                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 439                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 440                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 441                 >;
 442         };
 443
 444         pinctrl_i2c1: i2c1grp {
 445                 fsl,pins = <
 446                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 447                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 448                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0
 449                 >;
 450         };
 451
 452         pinctrl_i2c2: i2c2grp {
 453                 fsl,pins = <
 454                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 455                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 456                 >;
 457         };
 458
 459         pinctrl_i2c3: i2c3grp {
 460                 fsl,pins = <
 461                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 462                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 463                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b0
 464                         MX6QDL_PAD_GPIO_19__GPIO4_IO05          0x1b0b0
 465                 >;
 466         };
 467
 468         pinctrl_pcie: pciegrp {
 469                 fsl,pins = <
 470                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0
 471                 >;
 472         };
 473
 474         pinctrl_pps: ppsgrp {
 475                 fsl,pins = <
 476                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 477                 >;
 478         };
 479
 480         pinctrl_pwm2: pwm2grp {
 481                 fsl,pins = <
 482                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 483                 >;
 484         };
 485
 486         pinctrl_pwm3: pwm3grp {
 487                 fsl,pins = <
 488                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 489                 >;
 490         };
 491
 492         pinctrl_pwm4: pwm4grp {
 493                 fsl,pins = <
 494                         MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 495                 >;
 496         };
 497
 498         pinctrl_uart1: uart1grp {
 499                 fsl,pins = <
 500                         MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 501                         MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 502                 >;
 503         };
 504
 505         pinctrl_uart2: uart2grp {
 506                 fsl,pins = <
 507                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 508                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 509                 >;
 510         };
 511
 512         pinctrl_uart3: uart3grp {
 513                 fsl,pins = <
 514                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 515                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 516                 >;
 517         };
 518
 519         pinctrl_uart5: uart5grp {
 520                 fsl,pins = <
 521                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 522                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 523                 >;
 524         };
 525
 526         pinctrl_usbotg: usbotggrp {
 527                 fsl,pins = <
 528                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 529                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0
 530                 >;
 531         };
 532
 533         pinctrl_wdog: wdoggrp {
 534                 fsl,pins = <
 535                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 536                 >;
 537         };
 538 };