arch/arm/boot/dts/imx6qdl-gw553x.dtsi

   1 /*
   2  * Copyright 2016 Gateworks Corporation
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/gpio/gpio.h>
  49 #include <dt-bindings/input/linux-event-codes.h>
  50
  51 / {
  52         /* these are used by bootloader for disabling nodes */
  53         aliases {
  54                 led0 = &led0;
  55                 led1 = &led1;
  56                 nand = &gpmi;
  57                 usb0 = &usbh1;
  58                 usb1 = &usbotg;
  59         };
  60
  61         chosen {
  62                 stdout-path = &uart2;
  63         };
  64
  65         gpio-keys {
  66                 compatible = "gpio-keys";
  67                 #address-cells = <1>;
  68                 #size-cells = <0>;
  69
  70                 user-pb {
  71                         label = "user_pb";
  72                         gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  73                         linux,code = <BTN_0>;
  74                 };
  75
  76                 user-pb1x {
  77                         label = "user_pb1x";
  78                         linux,code = <BTN_1>;
  79                         interrupt-parent = <&gsc>;
  80                         interrupts = <0>;
  81                 };
  82
  83                 key-erased {
  84                         label = "key-erased";
  85                         linux,code = <BTN_2>;
  86                         interrupt-parent = <&gsc>;
  87                         interrupts = <1>;
  88                 };
  89
  90                 eeprom-wp {
  91                         label = "eeprom_wp";
  92                         linux,code = <BTN_3>;
  93                         interrupt-parent = <&gsc>;
  94                         interrupts = <2>;
  95                 };
  96
  97                 tamper {
  98                         label = "tamper";
  99                         linux,code = <BTN_4>;
 100                         interrupt-parent = <&gsc>;
 101                         interrupts = <5>;
 102                 };
 103
 104                 switch-hold {
 105                         label = "switch_hold";
 106                         linux,code = <BTN_5>;
 107                         interrupt-parent = <&gsc>;
 108                         interrupts = <7>;
 109                 };
 110         };
 111
 112         leds {
 113                 compatible = "gpio-leds";
 114                 pinctrl-names = "default";
 115                 pinctrl-0 = <&pinctrl_gpio_leds>;
 116
 117                 led0: user1 {
 118                         label = "user1";
 119                         gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
 120                         default-state = "on";
 121                         linux,default-trigger = "heartbeat";
 122                 };
 123
 124                 led1: user2 {
 125                         label = "user2";
 126                         gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
 127                         default-state = "off";
 128                 };
 129         };
 130
 131         memory@10000000 {
 132                 device_type = "memory";
 133                 reg = <0x10000000 0x20000000>;
 134         };
 135
 136         pps {
 137                 compatible = "pps-gpio";
 138                 pinctrl-names = "default";
 139                 pinctrl-0 = <&pinctrl_pps>;
 140                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 141                 status = "okay";
 142         };
 143
 144         reg_5p0v: regulator-5p0v {
 145                 compatible = "regulator-fixed";
 146                 regulator-name = "5P0V";
 147                 regulator-min-microvolt = <5000000>;
 148                 regulator-max-microvolt = <5000000>;
 149                 regulator-always-on;
 150         };
 151
 152         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 153                 compatible = "regulator-fixed";
 154                 regulator-name = "usb_otg_vbus";
 155                 regulator-min-microvolt = <5000000>;
 156                 regulator-max-microvolt = <5000000>;
 157                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 158                 enable-active-high;
 159         };
 160 };
 161
 162 &gpmi {
 163         pinctrl-names = "default";
 164         pinctrl-0 = <&pinctrl_gpmi_nand>;
 165         status = "okay";
 166 };
 167
 168 &hdmi {
 169         pinctrl-names = "default";
 170         pinctrl-0 = <&pinctrl_hdmi>;
 171         ddc-i2c-bus = <&i2c3>;
 172         status = "okay";
 173 };
 174
 175 &i2c1 {
 176         clock-frequency = <100000>;
 177         pinctrl-names = "default";
 178         pinctrl-0 = <&pinctrl_i2c1>;
 179         status = "okay";
 180
 181         gsc: gsc@20 {
 182                 compatible = "gw,gsc";
 183                 reg = <0x20>;
 184                 interrupt-parent = <&gpio1>;
 185                 interrupts = <4 GPIO_ACTIVE_LOW>;
 186                 interrupt-controller;
 187                 #interrupt-cells = <1>;
 188                 #size-cells = <0>;
 189
 190                 adc {
 191                         compatible = "gw,gsc-adc";
 192                         #address-cells = <1>;
 193                         #size-cells = <0>;
 194
 195                         channel@0 {
 196                                 gw,mode = <0>;
 197                                 reg = <0x00>;
 198                                 label = "temp";
 199                         };
 200
 201                         channel@2 {
 202                                 gw,mode = <1>;
 203                                 reg = <0x02>;
 204                                 label = "vdd_vin";
 205                         };
 206
 207                         channel@5 {
 208                                 gw,mode = <1>;
 209                                 reg = <0x05>;
 210                                 label = "vdd_3p3";
 211                         };
 212
 213                         channel@8 {
 214                                 gw,mode = <1>;
 215                                 reg = <0x08>;
 216                                 label = "vdd_bat";
 217                         };
 218
 219                         channel@b {
 220                                 gw,mode = <1>;
 221                                 reg = <0x0b>;
 222                                 label = "vdd_5p0";
 223                         };
 224
 225                         channel@e {
 226                                 gw,mode = <1>;
 227                                 reg = <0xe>;
 228                                 label = "vdd_arm";
 229                         };
 230
 231                         channel@11 {
 232                                 gw,mode = <1>;
 233                                 reg = <0x11>;
 234                                 label = "vdd_soc";
 235                         };
 236
 237                         channel@14 {
 238                                 gw,mode = <1>;
 239                                 reg = <0x14>;
 240                                 label = "vdd_3p0";
 241                         };
 242
 243                         channel@17 {
 244                                 gw,mode = <1>;
 245                                 reg = <0x17>;
 246                                 label = "vdd_1p5";
 247                         };
 248
 249                         channel@1d {
 250                                 gw,mode = <1>;
 251                                 reg = <0x1d>;
 252                                 label = "vdd_1p8a";
 253                         };
 254
 255                         channel@20 {
 256                                 gw,mode = <1>;
 257                                 reg = <0x20>;
 258                                 label = "vdd_1p0b";
 259                         };
 260
 261                         channel@26 {
 262                                 gw,mode = <1>;
 263                                 reg = <0x26>;
 264                                 label = "vdd_an1";
 265                         };
 266                 };
 267         };
 268
 269         gsc_gpio: gpio@23 {
 270                 compatible = "nxp,pca9555";
 271                 reg = <0x23>;
 272                 gpio-controller;
 273                 #gpio-cells = <2>;
 274                 interrupt-parent = <&gsc>;
 275                 interrupts = <4>;
 276         };
 277
 278         eeprom1: eeprom@50 {
 279                 compatible = "atmel,24c02";
 280                 reg = <0x50>;
 281                 pagesize = <16>;
 282         };
 283
 284         eeprom2: eeprom@51 {
 285                 compatible = "atmel,24c02";
 286                 reg = <0x51>;
 287                 pagesize = <16>;
 288         };
 289
 290         eeprom3: eeprom@52 {
 291                 compatible = "atmel,24c02";
 292                 reg = <0x52>;
 293                 pagesize = <16>;
 294         };
 295
 296         eeprom4: eeprom@53 {
 297                 compatible = "atmel,24c02";
 298                 reg = <0x53>;
 299                 pagesize = <16>;
 300         };
 301
 302         rtc: ds1672@68 {
 303                 compatible = "dallas,ds1672";
 304                 reg = <0x68>;
 305         };
 306 };
 307
 308 &i2c2 {
 309         clock-frequency = <100000>;
 310         pinctrl-names = "default";
 311         pinctrl-0 = <&pinctrl_i2c2>;
 312         status = "okay";
 313
 314         magn@1c {
 315                 compatible = "st,lsm9ds1-magn";
 316                 reg = <0x1c>;
 317                 pinctrl-names = "default";
 318                 pinctrl-0 = <&pinctrl_mag>;
 319                 interrupt-parent = <&gpio1>;
 320                 interrupts = <2 IRQ_TYPE_EDGE_RISING>;
 321         };
 322
 323         imu@6a {
 324                 compatible = "st,lsm9ds1-imu";
 325                 reg = <0x6a>;
 326                 st,drdy-int-pin = <1>;
 327                 pinctrl-names = "default";
 328                 pinctrl-0 = <&pinctrl_imu>;
 329                 interrupt-parent = <&gpio7>;
 330                 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
 331         };
 332
 333         ltc3676: pmic@3c {
 334                 compatible = "lltc,ltc3676";
 335                 reg = <0x3c>;
 336                 pinctrl-names = "default";
 337                 pinctrl-0 = <&pinctrl_pmic>;
 338                 interrupt-parent = <&gpio1>;
 339                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 340
 341                 regulators {
 342                         /* VDD_SOC (1+R1/R2 = 1.635) */
 343                         reg_vdd_soc: sw1 {
 344                                 regulator-name = "vddsoc";
 345                                 regulator-min-microvolt = <674400>;
 346                                 regulator-max-microvolt = <1308000>;
 347                                 lltc,fb-voltage-divider = <127000 200000>;
 348                                 regulator-ramp-delay = <7000>;
 349                                 regulator-boot-on;
 350                                 regulator-always-on;
 351                         };
 352
 353                         /* VDD_DDR (1+R1/R2 = 2.105) */
 354                         reg_vdd_ddr: sw2 {
 355                                 regulator-name = "vddddr";
 356                                 regulator-min-microvolt = <868310>;
 357                                 regulator-max-microvolt = <1684000>;
 358                                 lltc,fb-voltage-divider = <221000 200000>;
 359                                 regulator-ramp-delay = <7000>;
 360                                 regulator-boot-on;
 361                                 regulator-always-on;
 362                         };
 363
 364                         /* VDD_ARM (1+R1/R2 = 1.635) */
 365                         reg_vdd_arm: sw3 {
 366                                 regulator-name = "vddarm";
 367                                 regulator-min-microvolt = <674400>;
 368                                 regulator-max-microvolt = <1308000>;
 369                                 lltc,fb-voltage-divider = <127000 200000>;
 370                                 regulator-ramp-delay = <7000>;
 371                                 regulator-boot-on;
 372                                 regulator-always-on;
 373                         };
 374
 375                         /* VDD_3P3 (1+R1/R2 = 1.281) */
 376                         reg_3p3v: sw4 {
 377                                 regulator-name = "vdd3p3";
 378                                 regulator-min-microvolt = <1880000>;
 379                                 regulator-max-microvolt = <3647000>;
 380                                 lltc,fb-voltage-divider = <200000 56200>;
 381                                 regulator-ramp-delay = <7000>;
 382                                 regulator-boot-on;
 383                                 regulator-always-on;
 384                         };
 385
 386                         /* VDD_1P8a (1+R1/R2 = 2.505): Analog Video Decoder */
 387                         reg_1p8a: ldo2 {
 388                                 regulator-name = "vdd1p8a";
 389                                 regulator-min-microvolt = <1816125>;
 390                                 regulator-max-microvolt = <1816125>;
 391                                 lltc,fb-voltage-divider = <301000 200000>;
 392                                 regulator-boot-on;
 393                                 regulator-always-on;
 394                         };
 395
 396                         /* VDD_1P8b: microSD VDD_1P8 */
 397                         reg_1p8b: ldo3 {
 398                                 regulator-name = "vdd1p8b";
 399                                 regulator-min-microvolt = <1800000>;
 400                                 regulator-max-microvolt = <1800000>;
 401                                 regulator-boot-on;
 402                         };
 403
 404                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 405                         reg_3p0v: ldo4 {
 406                                 regulator-name = "vdd3p0";
 407                                 regulator-min-microvolt = <3023250>;
 408                                 regulator-max-microvolt = <3023250>;
 409                                 lltc,fb-voltage-divider = <634000 200000>;
 410                                 regulator-boot-on;
 411                                 regulator-always-on;
 412                         };
 413                 };
 414         };
 415 };
 416
 417 &i2c3 {
 418         clock-frequency = <100000>;
 419         pinctrl-names = "default";
 420         pinctrl-0 = <&pinctrl_i2c3>;
 421         status = "okay";
 422
 423         adv7180: camera@20 {
 424                 compatible = "adi,adv7180";
 425                 pinctrl-names = "default";
 426                 pinctrl-0 = <&pinctrl_adv7180>;
 427                 reg = <0x20>;
 428                 powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
 429                 interrupt-parent = <&gpio5>;
 430                 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
 431
 432                 port {
 433                         adv7180_to_ipu1_csi0_mux: endpoint {
 434                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
 435                                 bus-width = <8>;
 436                         };
 437                 };
 438         };
 439 };
 440
 441 &ipu1_csi0_from_ipu1_csi0_mux {
 442         bus-width = <8>;
 443 };
 444
 445 &ipu1_csi0_mux_from_parallel_sensor {
 446         remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
 447         bus-width = <8>;
 448 };
 449
 450 &ipu1_csi0 {
 451         pinctrl-names = "default";
 452         pinctrl-0 = <&pinctrl_ipu1_csi0>;
 453 };
 454
 455 &pcie {
 456         pinctrl-names = "default";
 457         pinctrl-0 = <&pinctrl_pcie>;
 458         reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 459         status = "okay";
 460 };
 461
 462 &pwm2 {
 463         pinctrl-names = "default";
 464         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 465         status = "disabled";
 466 };
 467
 468 &pwm3 {
 469         pinctrl-names = "default";
 470         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 471         status = "disabled";
 472 };
 473
 474 &pwm4 {
 475         pinctrl-names = "default";
 476         pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
 477         status = "disabled";
 478 };
 479
 480 &uart2 {
 481         pinctrl-names = "default";
 482         pinctrl-0 = <&pinctrl_uart2>;
 483         status = "okay";
 484 };
 485
 486 &uart3 {
 487         pinctrl-names = "default";
 488         pinctrl-0 = <&pinctrl_uart3>;
 489         status = "okay";
 490 };
 491
 492 &uart4 {
 493         pinctrl-names = "default";
 494         pinctrl-0 = <&pinctrl_uart4>;
 495         status = "okay";
 496 };
 497
 498 &uart5 {
 499         pinctrl-names = "default";
 500         pinctrl-0 = <&pinctrl_uart5>;
 501         status = "okay";
 502 };
 503
 504 &usbh1 {
 505         status = "okay";
 506 };
 507
 508 &usbotg {
 509         vbus-supply = <&reg_usb_otg_vbus>;
 510         pinctrl-names = "default";
 511         pinctrl-0 = <&pinctrl_usbotg>;
 512         disable-over-current;
 513         status = "okay";
 514 };
 515
 516 &usdhc3 {
 517         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 518         pinctrl-0 = <&pinctrl_usdhc3>;
 519         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 520         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 521         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 522         status = "okay";
 523 };
 524
 525 &wdog1 {
 526         pinctrl-names = "default";
 527         pinctrl-0 = <&pinctrl_wdog>;
 528         fsl,ext-reset-output;
 529 };
 530
 531 &iomuxc {
 532         pinctrl_adv7180: adv7180grp {
 533                 fsl,pins = <
 534                         MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23        0x0001b0b0
 535                         MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20     0x4001b0b0
 536                 >;
 537         };
 538
 539         pinctrl_gpmi_nand: gpminandgrp {
 540                 fsl,pins = <
 541                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 542                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 543                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 544                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 545                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 546                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 547                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 548                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 549                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 550                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 551                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 552                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 553                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 554                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 555                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 556                 >;
 557         };
 558
 559         pinctrl_hdmi: hdmigrp {
 560                 fsl,pins = <
 561                         MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE    0x1f8b0
 562                 >;
 563         };
 564
 565         pinctrl_i2c1: i2c1grp {
 566                 fsl,pins = <
 567                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 568                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 569                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0xb0b1
 570                 >;
 571         };
 572
 573         pinctrl_i2c2: i2c2grp {
 574                 fsl,pins = <
 575                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 576                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 577                 >;
 578         };
 579
 580         pinctrl_i2c3: i2c3grp {
 581                 fsl,pins = <
 582                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 583                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 584                 >;
 585         };
 586
 587         pinctrl_imu: imugrp {
 588                 fsl,pins = <
 589                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x1b0b0
 590                 >;
 591         };
 592
 593         pinctrl_ipu1_csi0: ipu1csi0grp {
 594                 fsl,pins = <
 595                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
 596                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
 597                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
 598                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
 599                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
 600                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
 601                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
 602                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
 603                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
 604                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
 605                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
 606                 >;
 607         };
 608
 609         pinctrl_gpio_leds: gpioledsgrp {
 610                 fsl,pins = <
 611                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10         0x1b0b0
 612                         MX6QDL_PAD_KEY_ROW2__GPIO4_IO11         0x1b0b0
 613                 >;
 614         };
 615
 616         pinctrl_mag: maggrp {
 617                 fsl,pins = <
 618                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b0
 619                 >;
 620         };
 621
 622         pinctrl_pcie: pciegrp {
 623                 fsl,pins = <
 624                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0
 625                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x4001b0b0 /* PCIESKT_WDIS# */
 626                 >;
 627         };
 628
 629         pinctrl_pmic: pmicgrp {
 630                 fsl,pins = <
 631                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0001b0b0 /* PMIC_IRQ# */
 632                 >;
 633         };
 634
 635         pinctrl_pps: ppsgrp {
 636                 fsl,pins = <
 637                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 638                 >;
 639         };
 640
 641         pinctrl_pwm2: pwm2grp {
 642                 fsl,pins = <
 643                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 644                 >;
 645         };
 646
 647         pinctrl_pwm3: pwm3grp {
 648                 fsl,pins = <
 649                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 650                 >;
 651         };
 652
 653         pinctrl_pwm4: pwm4grp {
 654                 fsl,pins = <
 655                         MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 656                 >;
 657         };
 658
 659         pinctrl_uart2: uart2grp {
 660                 fsl,pins = <
 661                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 662                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 663                 >;
 664         };
 665
 666         pinctrl_uart3: uart3grp {
 667                 fsl,pins = <
 668                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 669                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 670                 >;
 671         };
 672
 673         pinctrl_uart4: uart4grp {
 674                 fsl,pins = <
 675                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 676                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 677                 >;
 678         };
 679
 680         pinctrl_uart5: uart5grp {
 681                 fsl,pins = <
 682                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 683                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 684                 >;
 685         };
 686
 687         pinctrl_usbotg: usbotggrp {
 688                 fsl,pins = <
 689                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 690                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* OTG_PWR_EN */
 691                 >;
 692         };
 693
 694         pinctrl_usdhc3: usdhc3grp {
 695                 fsl,pins = <
 696                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 697                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 698                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 699                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 700                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 701                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 702                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 703                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 704                 >;
 705         };
 706
 707         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 708                 fsl,pins = <
 709                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 710                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 711                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 712                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 713                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 714                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 715                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 716                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 717                 >;
 718         };
 719
 720         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 721                 fsl,pins = <
 722                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 723                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 724                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 725                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 726                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 727                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 728                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 729                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 730                 >;
 731         };
 732
 733         pinctrl_wdog: wdoggrp {
 734                 fsl,pins = <
 735                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 736                 >;
 737         };
 738 };