arch/arm/boot/dts/imx6qdl-gw51xx.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2013 Gateworks Corporation
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/linux-event-codes.h>
   8
   9 / {
  10         /* these are used by bootloader for disabling nodes */
  11         aliases {
  12                 led0 = &led0;
  13                 led1 = &led1;
  14                 nand = &gpmi;
  15                 usb0 = &usbh1;
  16                 usb1 = &usbotg;
  17         };
  18
  19         chosen {
  20                 bootargs = "console=ttymxc1,115200";
  21         };
  22
  23         gpio-keys {
  24                 compatible = "gpio-keys";
  25
  26                 user-pb {
  27                         label = "user_pb";
  28                         gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  29                         linux,code = <BTN_0>;
  30                 };
  31
  32                 user-pb1x {
  33                         label = "user_pb1x";
  34                         linux,code = <BTN_1>;
  35                         interrupt-parent = <&gsc>;
  36                         interrupts = <0>;
  37                 };
  38
  39                 key-erased {
  40                         label = "key-erased";
  41                         linux,code = <BTN_2>;
  42                         interrupt-parent = <&gsc>;
  43                         interrupts = <1>;
  44                 };
  45
  46                 eeprom-wp {
  47                         label = "eeprom_wp";
  48                         linux,code = <BTN_3>;
  49                         interrupt-parent = <&gsc>;
  50                         interrupts = <2>;
  51                 };
  52
  53                 tamper {
  54                         label = "tamper";
  55                         linux,code = <BTN_4>;
  56                         interrupt-parent = <&gsc>;
  57                         interrupts = <5>;
  58                 };
  59
  60                 switch-hold {
  61                         label = "switch_hold";
  62                         linux,code = <BTN_5>;
  63                         interrupt-parent = <&gsc>;
  64                         interrupts = <7>;
  65                 };
  66         };
  67
  68         leds {
  69                 compatible = "gpio-leds";
  70                 pinctrl-names = "default";
  71                 pinctrl-0 = <&pinctrl_gpio_leds>;
  72
  73                 led0: user1 {
  74                         label = "user1";
  75                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  76                         default-state = "on";
  77                         linux,default-trigger = "heartbeat";
  78                 };
  79
  80                 led1: user2 {
  81                         label = "user2";
  82                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  83                         default-state = "off";
  84                 };
  85         };
  86
  87         memory@10000000 {
  88                 device_type = "memory";
  89                 reg = <0x10000000 0x20000000>;
  90         };
  91
  92         pps {
  93                 compatible = "pps-gpio";
  94                 pinctrl-names = "default";
  95                 pinctrl-0 = <&pinctrl_pps>;
  96                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  97                 status = "okay";
  98         };
  99
 100         reg_3p3v: regulator-3p3v {
 101                 compatible = "regulator-fixed";
 102                 regulator-name = "3P3V";
 103                 regulator-min-microvolt = <3300000>;
 104                 regulator-max-microvolt = <3300000>;
 105                 regulator-always-on;
 106         };
 107
 108         reg_5p0v: regulator-5p0v {
 109                 compatible = "regulator-fixed";
 110                 regulator-name = "5P0V";
 111                 regulator-min-microvolt = <5000000>;
 112                 regulator-max-microvolt = <5000000>;
 113                 regulator-always-on;
 114         };
 115
 116         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 117                 compatible = "regulator-fixed";
 118                 regulator-name = "usb_otg_vbus";
 119                 regulator-min-microvolt = <5000000>;
 120                 regulator-max-microvolt = <5000000>;
 121                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 122                 enable-active-high;
 123         };
 124 };
 125
 126 &fec {
 127         pinctrl-names = "default";
 128         pinctrl-0 = <&pinctrl_enet>;
 129         phy-mode = "rgmii-id";
 130         phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 131         status = "okay";
 132 };
 133
 134 &gpmi {
 135         pinctrl-names = "default";
 136         pinctrl-0 = <&pinctrl_gpmi_nand>;
 137         status = "okay";
 138 };
 139
 140 &hdmi {
 141         ddc-i2c-bus = <&i2c3>;
 142         status = "okay";
 143 };
 144
 145 &i2c1 {
 146         clock-frequency = <100000>;
 147         pinctrl-names = "default";
 148         pinctrl-0 = <&pinctrl_i2c1>;
 149         status = "okay";
 150
 151         gsc: gsc@20 {
 152                 compatible = "gw,gsc";
 153                 reg = <0x20>;
 154                 interrupt-parent = <&gpio1>;
 155                 interrupts = <4 GPIO_ACTIVE_LOW>;
 156                 interrupt-controller;
 157                 #interrupt-cells = <1>;
 158                 #size-cells = <0>;
 159
 160                 adc {
 161                         compatible = "gw,gsc-adc";
 162                         #address-cells = <1>;
 163                         #size-cells = <0>;
 164
 165                         channel@0 {
 166                                 gw,mode = <0>;
 167                                 reg = <0x00>;
 168                                 label = "temp";
 169                         };
 170
 171                         channel@2 {
 172                                 gw,mode = <1>;
 173                                 reg = <0x02>;
 174                                 label = "vdd_vin";
 175                         };
 176
 177                         channel@5 {
 178                                 gw,mode = <1>;
 179                                 reg = <0x05>;
 180                                 label = "vdd_3p3";
 181                         };
 182
 183                         channel@8 {
 184                                 gw,mode = <1>;
 185                                 reg = <0x08>;
 186                                 label = "vdd_bat";
 187                         };
 188
 189                         channel@b {
 190                                 gw,mode = <1>;
 191                                 reg = <0x0b>;
 192                                 label = "vdd_5p0";
 193                         };
 194
 195                         channel@e {
 196                                 gw,mode = <1>;
 197                                 reg = <0xe>;
 198                                 label = "vdd_arm";
 199                         };
 200
 201                         channel@11 {
 202                                 gw,mode = <1>;
 203                                 reg = <0x11>;
 204                                 label = "vdd_soc";
 205                         };
 206
 207                         channel@14 {
 208                                 gw,mode = <1>;
 209                                 reg = <0x14>;
 210                                 label = "vdd_3p0";
 211                         };
 212
 213                         channel@17 {
 214                                 gw,mode = <1>;
 215                                 reg = <0x17>;
 216                                 label = "vdd_1p5";
 217                         };
 218
 219                         channel@1d {
 220                                 gw,mode = <1>;
 221                                 reg = <0x1d>;
 222                                 label = "vdd_1p8";
 223                         };
 224
 225                         channel@20 {
 226                                 gw,mode = <1>;
 227                                 reg = <0x20>;
 228                                 label = "vdd_an1";
 229                         };
 230
 231                         channel@23 {
 232                                 gw,mode = <1>;
 233                                 reg = <0x23>;
 234                                 label = "vdd_2p5";
 235                         };
 236                 };
 237         };
 238
 239         gsc_gpio: gpio@23 {
 240                 compatible = "nxp,pca9555";
 241                 reg = <0x23>;
 242                 gpio-controller;
 243                 #gpio-cells = <2>;
 244                 interrupt-parent = <&gsc>;
 245                 interrupts = <4>;
 246         };
 247
 248         eeprom1: eeprom@50 {
 249                 compatible = "atmel,24c02";
 250                 reg = <0x50>;
 251                 pagesize = <16>;
 252         };
 253
 254         eeprom2: eeprom@51 {
 255                 compatible = "atmel,24c02";
 256                 reg = <0x51>;
 257                 pagesize = <16>;
 258         };
 259
 260         eeprom3: eeprom@52 {
 261                 compatible = "atmel,24c02";
 262                 reg = <0x52>;
 263                 pagesize = <16>;
 264         };
 265
 266         eeprom4: eeprom@53 {
 267                 compatible = "atmel,24c02";
 268                 reg = <0x53>;
 269                 pagesize = <16>;
 270         };
 271
 272         rtc: ds1672@68 {
 273                 compatible = "dallas,ds1672";
 274                 reg = <0x68>;
 275         };
 276 };
 277
 278 &i2c2 {
 279         clock-frequency = <100000>;
 280         pinctrl-names = "default";
 281         pinctrl-0 = <&pinctrl_i2c2>;
 282         status = "okay";
 283
 284         ltc3676: pmic@3c {
 285                 compatible = "lltc,ltc3676";
 286                 reg = <0x3c>;
 287                 pinctrl-names = "default";
 288                 pinctrl-0 = <&pinctrl_pmic>;
 289                 interrupt-parent = <&gpio1>;
 290                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 291
 292                 regulators {
 293                         /* VDD_SOC (1+R1/R2 = 1.635) */
 294                         reg_vdd_soc: sw1 {
 295                                 regulator-name = "vddsoc";
 296                                 regulator-min-microvolt = <674400>;
 297                                 regulator-max-microvolt = <1308000>;
 298                                 lltc,fb-voltage-divider = <127000 200000>;
 299                                 regulator-ramp-delay = <7000>;
 300                                 regulator-boot-on;
 301                                 regulator-always-on;
 302                         };
 303
 304                         /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
 305                         reg_1p8v: sw2 {
 306                                 regulator-name = "vdd1p8";
 307                                 regulator-min-microvolt = <1033310>;
 308                                 regulator-max-microvolt = <2004000>;
 309                                 lltc,fb-voltage-divider = <301000 200000>;
 310                                 regulator-ramp-delay = <7000>;
 311                                 regulator-boot-on;
 312                                 regulator-always-on;
 313                         };
 314
 315                         /* VDD_ARM (1+R1/R2 = 1.635) */
 316                         reg_vdd_arm: sw3 {
 317                                 regulator-name = "vddarm";
 318                                 regulator-min-microvolt = <674400>;
 319                                 regulator-max-microvolt = <1308000>;
 320                                 lltc,fb-voltage-divider = <127000 200000>;
 321                                 regulator-ramp-delay = <7000>;
 322                                 regulator-boot-on;
 323                                 regulator-always-on;
 324                         };
 325
 326                         /* VDD_DDR (1+R1/R2 = 2.105) */
 327                         reg_vdd_ddr: sw4 {
 328                                 regulator-name = "vddddr";
 329                                 regulator-min-microvolt = <868310>;
 330                                 regulator-max-microvolt = <1684000>;
 331                                 lltc,fb-voltage-divider = <221000 200000>;
 332                                 regulator-ramp-delay = <7000>;
 333                                 regulator-boot-on;
 334                                 regulator-always-on;
 335                         };
 336
 337                         /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
 338                         reg_2p5v: ldo2 {
 339                                 regulator-name = "vdd2p5";
 340                                 regulator-min-microvolt = <2490375>;
 341                                 regulator-max-microvolt = <2490375>;
 342                                 lltc,fb-voltage-divider = <487000 200000>;
 343                                 regulator-boot-on;
 344                                 regulator-always-on;
 345                         };
 346
 347                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 348                         reg_3p0v: ldo4 {
 349                                 regulator-name = "vdd3p0";
 350                                 regulator-min-microvolt = <3023250>;
 351                                 regulator-max-microvolt = <3023250>;
 352                                 lltc,fb-voltage-divider = <634000 200000>;
 353                                 regulator-boot-on;
 354                                 regulator-always-on;
 355                         };
 356                 };
 357         };
 358 };
 359
 360 &i2c3 {
 361         clock-frequency = <100000>;
 362         pinctrl-names = "default";
 363         pinctrl-0 = <&pinctrl_i2c3>;
 364         status = "okay";
 365
 366         adv7180: camera@20 {
 367                 compatible = "adi,adv7180";
 368                 pinctrl-names = "default";
 369                 pinctrl-0 = <&pinctrl_adv7180>;
 370                 reg = <0x20>;
 371                 powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
 372                 interrupt-parent = <&gpio5>;
 373                 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
 374
 375                 port {
 376                         adv7180_to_ipu1_csi0_mux: endpoint {
 377                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
 378                                 bus-width = <8>;
 379                         };
 380                 };
 381         };
 382 };
 383
 384 &ipu1_csi0_from_ipu1_csi0_mux {
 385         bus-width = <8>;
 386 };
 387
 388 &ipu1_csi0_mux_from_parallel_sensor {
 389         remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
 390         bus-width = <8>;
 391 };
 392
 393 &ipu1_csi0 {
 394         pinctrl-names = "default";
 395         pinctrl-0 = <&pinctrl_ipu1_csi0>;
 396 };
 397
 398 &pcie {
 399         pinctrl-names = "default";
 400         pinctrl-0 = <&pinctrl_pcie>;
 401         reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 402         status = "okay";
 403 };
 404
 405 &pwm2 {
 406         pinctrl-names = "default";
 407         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 408         status = "disabled";
 409 };
 410
 411 &pwm3 {
 412         pinctrl-names = "default";
 413         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 414         status = "disabled";
 415 };
 416
 417 &pwm4 {
 418         pinctrl-names = "default";
 419         pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
 420         status = "disabled";
 421 };
 422
 423 &uart1 {
 424         pinctrl-names = "default";
 425         pinctrl-0 = <&pinctrl_uart1>;
 426         status = "okay";
 427 };
 428
 429 &uart2 {
 430         pinctrl-names = "default";
 431         pinctrl-0 = <&pinctrl_uart2>;
 432         status = "okay";
 433 };
 434
 435 &uart3 {
 436         pinctrl-names = "default";
 437         pinctrl-0 = <&pinctrl_uart3>;
 438         status = "okay";
 439 };
 440
 441 &uart5 {
 442         pinctrl-names = "default";
 443         pinctrl-0 = <&pinctrl_uart5>;
 444         status = "okay";
 445 };
 446
 447 &usbotg {
 448         vbus-supply = <&reg_usb_otg_vbus>;
 449         pinctrl-names = "default";
 450         pinctrl-0 = <&pinctrl_usbotg>;
 451         disable-over-current;
 452         status = "okay";
 453 };
 454
 455 &usbh1 {
 456         status = "okay";
 457 };
 458
 459 &wdog1 {
 460         pinctrl-names = "default";
 461         pinctrl-0 = <&pinctrl_wdog>;
 462         fsl,ext-reset-output;
 463 };
 464
 465 &iomuxc {
 466         pinctrl_adv7180: adv7180grp {
 467                 fsl,pins = <
 468                         MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23        0x0001b0b0
 469                         MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20     0x4001b0b0
 470                 >;
 471         };
 472
 473         pinctrl_enet: enetgrp {
 474                 fsl,pins = <
 475                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 476                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 477                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 478                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 479                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 480                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 481                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 482                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 483                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 484                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 485                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 486                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 487                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 488                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 489                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 490                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 491                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0 /* PHY Reset */
 492                 >;
 493         };
 494
 495         pinctrl_gpio_leds: gpioledsgrp {
 496                 fsl,pins = <
 497                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 498                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 499                 >;
 500         };
 501
 502         pinctrl_gpmi_nand: gpminandgrp {
 503                 fsl,pins = <
 504                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 505                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 506                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 507                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 508                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 509                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 510                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 511                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 512                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 513                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 514                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 515                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 516                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 517                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 518                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 519                 >;
 520         };
 521
 522         pinctrl_i2c1: i2c1grp {
 523                 fsl,pins = <
 524                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 525                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 526                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0 /* GSC_IRQ# */
 527                 >;
 528         };
 529
 530         pinctrl_i2c2: i2c2grp {
 531                 fsl,pins = <
 532                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 533                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 534                 >;
 535         };
 536
 537         pinctrl_i2c3: i2c3grp {
 538                 fsl,pins = <
 539                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 540                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 541                 >;
 542         };
 543
 544         pinctrl_ipu1_csi0: ipu1csi0grp {
 545                 fsl,pins = <
 546                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
 547                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
 548                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
 549                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
 550                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
 551                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
 552                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
 553                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
 554                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
 555                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
 556                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
 557                 >;
 558         };
 559
 560         pinctrl_pcie: pciegrp {
 561                 fsl,pins = <
 562                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0
 563                 >;
 564         };
 565
 566         pinctrl_pmic: pmicgrp {
 567                 fsl,pins = <
 568                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0001b0b0 /* PMIC_IRQ# */
 569                 >;
 570         };
 571
 572         pinctrl_pps: ppsgrp {
 573                 fsl,pins = <
 574                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 575                 >;
 576         };
 577
 578         pinctrl_pwm2: pwm2grp {
 579                 fsl,pins = <
 580                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 581                 >;
 582         };
 583
 584         pinctrl_pwm3: pwm3grp {
 585                 fsl,pins = <
 586                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 587                 >;
 588         };
 589
 590         pinctrl_pwm4: pwm4grp {
 591                 fsl,pins = <
 592                         MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 593                 >;
 594         };
 595
 596         pinctrl_uart1: uart1grp {
 597                 fsl,pins = <
 598                         MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 599                         MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 600                 >;
 601         };
 602
 603         pinctrl_uart2: uart2grp {
 604                 fsl,pins = <
 605                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 606                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 607                 >;
 608         };
 609
 610         pinctrl_uart3: uart3grp {
 611                 fsl,pins = <
 612                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 613                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 614                 >;
 615         };
 616
 617         pinctrl_uart5: uart5grp {
 618                 fsl,pins = <
 619                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 620                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 621                 >;
 622         };
 623
 624         pinctrl_usbotg: usbotggrp {
 625                 fsl,pins = <
 626                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 627                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* OTG_PWR_EN */
 628                 >;
 629         };
 630
 631         pinctrl_wdog: wdoggrp {
 632                 fsl,pins = <
 633                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 634                 >;
 635         };
 636 };