arch/arm/boot/dts/imx6q-dhcom-pdk2.dts

   1 // SPDX-License-Identifier: (GPL-2.0+)
   2 /*
   3  * Copyright (C) 2015 DH electronics GmbH
   4  * Copyright (C) 2018 Marek Vasut <marex@denx.de>
   5  */
   6
   7 /dts-v1/;
   8
   9 #include "imx6q-dhcom-som.dtsi"
  10 #include <dt-bindings/leds/common.h>
  11
  12 / {
  13         model = "Freescale i.MX6 Quad DHCOM Premium Developer Kit (2)";
  14         compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som", "fsl,imx6q";
  15
  16         chosen {
  17                 stdout-path = "serial0:115200n8";
  18         };
  19
  20         clk_ext_audio_codec: clock-codec {
  21                 compatible = "fixed-clock";
  22                 #clock-cells = <0>;
  23                 clock-frequency = <24000000>;
  24         };
  25
  26         display_bl: display-bl {
  27                 compatible = "pwm-backlight";
  28                 pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>;
  29                 brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
  30                 default-brightness-level = <8>;
  31                 enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
  32                 status = "okay";
  33         };
  34
  35         lcd_display: disp0 {
  36                 compatible = "fsl,imx-parallel-display";
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39                 interface-pix-fmt = "rgb24";
  40                 pinctrl-names = "default";
  41                 pinctrl-0 = <&pinctrl_ipu1_lcdif>;
  42                 status = "okay";
  43
  44                 port@0 {
  45                         reg = <0>;
  46
  47                         lcd_display_in: endpoint {
  48                                 remote-endpoint = <&ipu1_di0_disp0>;
  49                         };
  50                 };
  51
  52                 port@1 {
  53                         reg = <1>;
  54
  55                         lcd_display_out: endpoint {
  56                                 remote-endpoint = <&lcd_panel_in>;
  57                         };
  58                 };
  59         };
  60
  61         gpio-keys {
  62                 #size-cells = <0>;
  63                 compatible = "gpio-keys";
  64                 pinctrl-names = "default";
  65                 pinctrl-0 = <&pinctrl_keys_pdk2>;
  66
  67                 button-0 {
  68                         label = "TA1-GPIO-A";
  69                         linux,code = <KEY_A>;
  70                         gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
  71                         wakeup-source;
  72                 };
  73
  74                 button-1 {
  75                         label = "TA2-GPIO-B";
  76                         linux,code = <KEY_B>;
  77                         gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
  78                         wakeup-source;
  79                 };
  80
  81                 button-2 {
  82                         label = "TA3-GPIO-C";
  83                         linux,code = <KEY_C>;
  84                         gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
  85                         wakeup-source;
  86                 };
  87
  88                 button-3 {
  89                         label = "TA4-GPIO-D";
  90                         linux,code = <KEY_D>;
  91                         gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
  92                         wakeup-source;
  93                 };
  94         };
  95
  96         led {
  97                 compatible = "gpio-leds";
  98                 pinctrl-names = "default";
  99                 pinctrl-0 = <&pinctrl_leds_pdk2>;
 100
 101                 /*
 102                  * Disable led-5, because GPIO E is
 103                  * already used as touch interrupt.
 104                  */
 105                 led-5 {
 106                         color = <LED_COLOR_ID_GREEN>;
 107                         function = LED_FUNCTION_INDICATOR;
 108                         gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */
 109                         default-state = "off";
 110                         status = "disabled";
 111                 };
 112
 113                 led-6 {
 114                         color = <LED_COLOR_ID_GREEN>;
 115                         function = LED_FUNCTION_INDICATOR;
 116                         gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */
 117                         default-state = "off";
 118                 };
 119
 120                 led-7 {
 121                         color = <LED_COLOR_ID_GREEN>;
 122                         function = LED_FUNCTION_INDICATOR;
 123                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */
 124                         default-state = "off";
 125                 };
 126
 127                 led-8 {
 128                         color = <LED_COLOR_ID_GREEN>;
 129                         function = LED_FUNCTION_INDICATOR;
 130                         gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
 131                         default-state = "off";
 132                 };
 133         };
 134
 135         panel {
 136                 compatible = "edt,etm0700g0edh6";
 137                 backlight = <&display_bl>;
 138
 139                 port {
 140                         lcd_panel_in: endpoint {
 141                                 remote-endpoint = <&lcd_display_out>;
 142                         };
 143                 };
 144         };
 145
 146         sound {
 147                 compatible = "fsl,imx-audio-sgtl5000";
 148                 model = "imx-sgtl5000";
 149                 ssi-controller = <&ssi1>;
 150                 audio-codec = <&sgtl5000>;
 151                 audio-routing =
 152                         "MIC_IN", "Mic Jack",
 153                         "Mic Jack", "Mic Bias",
 154                         "LINE_IN", "Line In Jack",
 155                         "Headphone Jack", "HP_OUT";
 156                 mux-int-port = <1>;
 157                 mux-ext-port = <3>;
 158         };
 159 };
 160
 161 &audmux {
 162         pinctrl-names = "default";
 163         pinctrl-0 = <&pinctrl_audmux_ext>;
 164         status = "okay";
 165 };
 166
 167 &can1 {
 168         status = "okay";
 169 };
 170
 171 &can2 {
 172         status = "disabled";
 173 };
 174
 175 /* 1G ethernet */
 176 /delete-node/ &ethphy0;
 177 &fec {
 178         phy-mode = "rgmii";
 179         phy-handle = <&ethphy7>;
 180         pinctrl-names = "default";
 181         pinctrl-0 = <&pinctrl_enet_1G>;
 182         status = "okay";
 183
 184         mdio {
 185                 #address-cells = <1>;
 186                 #size-cells = <0>;
 187
 188                 ethphy7: ethernet-phy@7 { /* KSZ 9021 */
 189                         compatible = "ethernet-phy-ieee802.3-c22";
 190                         interrupt-parent = <&gpio1>;
 191                         interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
 192                         pinctrl-0 = <&pinctrl_ethphy7>;
 193                         pinctrl-names = "default";
 194                         reg = <7>;
 195                         reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
 196                         reset-assert-us = <1000>;
 197                         reset-deassert-us = <1000>;
 198                         rxc-skew-ps = <3000>;
 199                         rxd0-skew-ps = <0>;
 200                         rxd1-skew-ps = <0>;
 201                         rxd2-skew-ps = <0>;
 202                         rxd3-skew-ps = <0>;
 203                         txc-skew-ps = <3000>;
 204                         txd0-skew-ps = <0>;
 205                         txd1-skew-ps = <0>;
 206                         txd2-skew-ps = <0>;
 207                         txd3-skew-ps = <0>;
 208                         rxdv-skew-ps = <0>;
 209                         txen-skew-ps = <0>;
 210                 };
 211         };
 212 };
 213
 214 &hdmi {
 215         ddc-i2c-bus = <&i2c2>;
 216         status = "okay";
 217 };
 218
 219 &i2c2 {
 220         sgtl5000: codec@a {
 221                 compatible = "fsl,sgtl5000";
 222                 reg = <0x0a>;
 223                 #sound-dai-cells = <0>;
 224                 clocks = <&clk_ext_audio_codec>;
 225                 VDDA-supply = <&reg_3p3v>;
 226                 VDDIO-supply = <&sw2_reg>;
 227         };
 228
 229         touchscreen@38 {
 230                 pinctrl-names = "default";
 231                 pinctrl-0 = <&pinctrl_touchscreen>;
 232                 compatible = "edt,edt-ft5406";
 233                 reg = <0x38>;
 234                 interrupt-parent = <&gpio4>;
 235                 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
 236         };
 237 };
 238
 239 &iomuxc {
 240         pinctrl-names = "default";
 241         pinctrl-0 = <&pinctrl_hog_base &pinctrl_hog>;
 242
 243         pinctrl_hog: hog-grp {
 244                 fsl,pins = <
 245                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x400120b0
 246                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x400120b0
 247                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x400120b0
 248                         MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03       0x400120b0
 249                         MX6QDL_PAD_DI0_PIN4__GPIO4_IO20         0x400120b0
 250                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x120b0
 251                         MX6QDL_PAD_KEY_COL1__GPIO4_IO08         0x400120b0
 252                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14        0x400120b0
 253                         MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x400120b0
 254                         MX6QDL_PAD_KEY_ROW1__GPIO4_IO09         0x400120b0
 255                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x400120b0
 256                         MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x400120b0
 257                         MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21       0x400120b0
 258                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x400120b0
 259                         MX6QDL_PAD_SD1_CMD__GPIO1_IO18          0x400120b0
 260                         MX6QDL_PAD_SD1_DAT0__GPIO1_IO16         0x400120b0
 261                         MX6QDL_PAD_SD1_DAT1__GPIO1_IO17         0x400120b0
 262                         MX6QDL_PAD_SD1_DAT2__GPIO1_IO19         0x400120b0
 263                         MX6QDL_PAD_SD1_CLK__GPIO1_IO20          0x400120b0
 264                         MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18      0x400120b0
 265                         MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19        0x400120b0
 266                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x400120b0
 267                 >;
 268         };
 269
 270         pinctrl_audmux_ext: audmux-ext-grp {
 271                 fsl,pins = <
 272                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 273                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 274                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 275                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 276                 >;
 277         };
 278
 279         pinctrl_enet_1G: enet-1G-grp {
 280                 fsl,pins = <
 281                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b0
 282                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x100b0
 283                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x100b0
 284                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x100b0
 285                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x100b0
 286                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x100b0
 287                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x100b0
 288                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x100b0
 289                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
 290                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 291                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 292                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 293                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 294                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 295                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 296                 >;
 297         };
 298
 299         pinctrl_ethphy7: ethphy7-grp {
 300                 fsl,pins = <
 301                         MX6QDL_PAD_EIM_D29__GPIO3_IO29          0xb0 /* Reset */
 302                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0xb1 /* Int */
 303                         MX6QDL_PAD_EIM_D26__GPIO3_IO26          0xb1 /* WOL */
 304                 >;
 305         };
 306
 307         pinctrl_ipu1_lcdif: ipu1-lcdif-grp {
 308                 fsl,pins = <
 309                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK      0x38
 310                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15            0x38
 311                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02             0x38
 312                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03             0x38
 313                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00        0x38
 314                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01        0x38
 315                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02        0x38
 316                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03        0x38
 317                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04        0x38
 318                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05        0x38
 319                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06        0x38
 320                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07        0x38
 321                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08        0x38
 322                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09        0x38
 323                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10       0x38
 324                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11       0x38
 325                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12       0x38
 326                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13       0x38
 327                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14       0x38
 328                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15       0x38
 329                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16       0x38
 330                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17       0x38
 331                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18       0x38
 332                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19       0x38
 333                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20       0x38
 334                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21       0x38
 335                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22       0x38
 336                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23       0x38
 337                         MX6QDL_PAD_EIM_D27__GPIO3_IO27                  0x120b0
 338                 >;
 339         };
 340
 341         pinctrl_pwm1: pwm1-grp {
 342                 fsl,pins = <
 343                         MX6QDL_PAD_SD1_DAT3__PWM1_OUT           0x1b0b1
 344                 >;
 345         };
 346
 347         pinctrl_touchscreen: touchscreen-grp {
 348                 fsl,pins = <
 349                         MX6QDL_PAD_GPIO_19__GPIO4_IO05          0x1b0b1
 350                 >;
 351         };
 352
 353         pinctrl_pcie_reset: pcie-reset-grp {
 354                 fsl,pins = <
 355                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14        0x120b0
 356                 >;
 357         };
 358
 359         pinctrl_keys_pdk2: keys-pdk2-grp {
 360                 fsl,pins = <
 361                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x120b0 /* TA1 */
 362                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x120b0 /* TA2 */
 363                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x120b0 /* TA3 */
 364                         MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03       0x120b0 /* TA4 */
 365                 >;
 366         };
 367
 368         pinctrl_leds_pdk2: leds-pdk2-grp {
 369                 fsl,pins = <
 370                         MX6QDL_PAD_DI0_PIN4__GPIO4_IO20         0x120b0 /* led6 */
 371                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x120b0 /* led7 */
 372                         MX6QDL_PAD_KEY_COL1__GPIO4_IO08         0x120b0 /* led8 */
 373                 >;
 374         };
 375
 376 };
 377
 378 &ipu1_di0_disp0 {
 379         remote-endpoint = <&lcd_display_in>;
 380 };
 381
 382 &pcie {
 383         pinctrl-0 = <&pinctrl_pcie &pinctrl_pcie_reset>;
 384         reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;
 385         status = "okay";
 386 };
 387
 388 &pwm1 {
 389         pinctrl-names = "default";
 390         pinctrl-0 = <&pinctrl_pwm1>;
 391         status = "okay";
 392 };
 393
 394 &ssi1 {
 395         status = "okay";
 396 };
 397
 398 &sata {
 399         status = "okay";
 400 };
 401
 402 &usdhc3 {
 403         status = "okay";
 404 };