arch/arm/boot/dts/am4372.dtsi

   1 /*
   2  * Device Tree Source for AM4372 SoC
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/bus/ti-sysc.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/clock/am4.h>
  15
  16 / {
  17         compatible = "ti,am4372", "ti,am43";
  18         interrupt-parent = <&wakeupgen>;
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21         chosen { };
  22
  23         memory@0 {
  24                 device_type = "memory";
  25                 reg = <0 0>;
  26         };
  27
  28         aliases {
  29                 i2c0 = &i2c0;
  30                 i2c1 = &i2c1;
  31                 i2c2 = &i2c2;
  32                 serial0 = &uart0;
  33                 serial1 = &uart1;
  34                 serial2 = &uart2;
  35                 serial3 = &uart3;
  36                 serial4 = &uart4;
  37                 serial5 = &uart5;
  38                 ethernet0 = &cpsw_port1;
  39                 ethernet1 = &cpsw_port2;
  40                 spi0 = &qspi;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46                 cpu: cpu@0 {
  47                         compatible = "arm,cortex-a9";
  48                         enable-method = "ti,am4372";
  49                         device_type = "cpu";
  50                         reg = <0>;
  51
  52                         clocks = <&dpll_mpu_ck>;
  53                         clock-names = "cpu";
  54
  55                         operating-points-v2 = <&cpu0_opp_table>;
  56
  57                         clock-latency = <300000>; /* From omap-cpufreq driver */
  58                         cpu-idle-states = <&mpu_gate>;
  59                 };
  60
  61                 idle-states {
  62                         mpu_gate: mpu_gate {
  63                                 compatible = "arm,idle-state";
  64                                 entry-latency-us = <40>;
  65                                 exit-latency-us = <100>;
  66                                 min-residency-us = <300>;
  67                                 local-timer-stop;
  68                         };
  69                 };
  70         };
  71
  72         cpu0_opp_table: opp-table {
  73                 compatible = "operating-points-v2-ti-cpu";
  74                 syscon = <&scm_conf>;
  75
  76                 opp50-300000000 {
  77                         opp-hz = /bits/ 64 <300000000>;
  78                         opp-microvolt = <950000 931000 969000>;
  79                         opp-supported-hw = <0xFF 0x01>;
  80                         opp-suspend;
  81                 };
  82
  83                 opp100-600000000 {
  84                         opp-hz = /bits/ 64 <600000000>;
  85                         opp-microvolt = <1100000 1078000 1122000>;
  86                         opp-supported-hw = <0xFF 0x04>;
  87                 };
  88
  89                 opp120-720000000 {
  90                         opp-hz = /bits/ 64 <720000000>;
  91                         opp-microvolt = <1200000 1176000 1224000>;
  92                         opp-supported-hw = <0xFF 0x08>;
  93                 };
  94
  95                 oppturbo-800000000 {
  96                         opp-hz = /bits/ 64 <800000000>;
  97                         opp-microvolt = <1260000 1234800 1285200>;
  98                         opp-supported-hw = <0xFF 0x10>;
  99                 };
 100
 101                 oppnitro-1000000000 {
 102                         opp-hz = /bits/ 64 <1000000000>;
 103                         opp-microvolt = <1325000 1298500 1351500>;
 104                         opp-supported-hw = <0xFF 0x20>;
 105                 };
 106         };
 107
 108         soc {
 109                 compatible = "ti,omap-infra";
 110                 mpu {
 111                         compatible = "ti,omap4-mpu";
 112                         ti,hwmods = "mpu";
 113                         pm-sram = <&pm_sram_code
 114                                    &pm_sram_data>;
 115                 };
 116         };
 117
 118         gic: interrupt-controller@48241000 {
 119                 compatible = "arm,cortex-a9-gic";
 120                 interrupt-controller;
 121                 #interrupt-cells = <3>;
 122                 reg = <0x48241000 0x1000>,
 123                       <0x48240100 0x0100>;
 124                 interrupt-parent = <&gic>;
 125         };
 126
 127         wakeupgen: interrupt-controller@48281000 {
 128                 compatible = "ti,omap4-wugen-mpu";
 129                 interrupt-controller;
 130                 #interrupt-cells = <3>;
 131                 reg = <0x48281000 0x1000>;
 132                 interrupt-parent = <&gic>;
 133         };
 134
 135         scu: scu@48240000 {
 136                 compatible = "arm,cortex-a9-scu";
 137                 reg = <0x48240000 0x100>;
 138         };
 139
 140         global_timer: timer@48240200 {
 141                 compatible = "arm,cortex-a9-global-timer";
 142                 reg = <0x48240200 0x100>;
 143                 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
 144                 interrupt-parent = <&gic>;
 145                 clocks = <&mpu_periphclk>;
 146         };
 147
 148         local_timer: timer@48240600 {
 149                 compatible = "arm,cortex-a9-twd-timer";
 150                 reg = <0x48240600 0x100>;
 151                 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
 152                 interrupt-parent = <&gic>;
 153                 clocks = <&mpu_periphclk>;
 154         };
 155
 156         cache-controller@48242000 {
 157                 compatible = "arm,pl310-cache";
 158                 reg = <0x48242000 0x1000>;
 159                 cache-unified;
 160                 cache-level = <2>;
 161         };
 162
 163         ocp@44000000 {
 164                 compatible = "ti,am4372-l3-noc", "simple-bus";
 165                 #address-cells = <1>;
 166                 #size-cells = <1>;
 167                 ranges;
 168                 ti,hwmods = "l3_main";
 169                 ti,no-idle;
 170                 reg = <0x44000000 0x400000
 171                        0x44800000 0x400000>;
 172                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 174
 175                 l4_wkup: interconnect@44c00000 {
 176                         wkup_m3: wkup_m3@100000 {
 177                                 compatible = "ti,am4372-wkup-m3";
 178                                 reg = <0x100000 0x4000>,
 179                                       <0x180000 0x2000>;
 180                                 reg-names = "umem", "dmem";
 181                                 ti,hwmods = "wkup_m3";
 182                                 ti,pm-firmware = "am335x-pm-firmware.elf";
 183                         };
 184                 };
 185                 l4_per: interconnect@48000000 {
 186                 };
 187                 l4_fast: interconnect@4a000000 {
 188                 };
 189
 190                 emif: emif@4c000000 {
 191                         compatible = "ti,emif-am4372";
 192                         reg = <0x4c000000 0x1000000>;
 193                         ti,hwmods = "emif";
 194                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 195                         ti,no-idle;
 196                         sram = <&pm_sram_code
 197                                 &pm_sram_data>;
 198                 };
 199
 200                 target-module@49000000 {
 201                         compatible = "ti,sysc-omap4", "ti,sysc";
 202                         reg = <0x49000000 0x4>;
 203                         reg-names = "rev";
 204                         clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
 205                         clock-names = "fck";
 206                         #address-cells = <1>;
 207                         #size-cells = <1>;
 208                         ranges = <0x0 0x49000000 0x10000>;
 209
 210                         edma: dma@0 {
 211                                 compatible = "ti,edma3-tpcc";
 212                                 reg = <0 0x10000>;
 213                                 reg-names = "edma3_cc";
 214                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 215                                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 216                                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 217                                 interrupt-names = "edma3_ccint", "edma3_mperr",
 218                                                   "edma3_ccerrint";
 219                                 dma-requests = <64>;
 220                                 #dma-cells = <2>;
 221
 222                                 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
 223                                            <&edma_tptc2 0>;
 224
 225                                 ti,edma-memcpy-channels = <58 59>;
 226                         };
 227                 };
 228
 229                 target-module@49800000 {
 230                         compatible = "ti,sysc-omap4", "ti,sysc";
 231                         reg = <0x49800000 0x4>,
 232                               <0x49800010 0x4>;
 233                         reg-names = "rev", "sysc";
 234                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 235                         ti,sysc-midle = <SYSC_IDLE_FORCE>;
 236                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 237                                         <SYSC_IDLE_SMART>;
 238                         clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
 239                         clock-names = "fck";
 240                         #address-cells = <1>;
 241                         #size-cells = <1>;
 242                         ranges = <0x0 0x49800000 0x100000>;
 243
 244                         edma_tptc0: dma@0 {
 245                                 compatible = "ti,edma3-tptc";
 246                                 reg = <0 0x100000>;
 247                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 248                                 interrupt-names = "edma3_tcerrint";
 249                         };
 250                 };
 251
 252                 target-module@49900000 {
 253                         compatible = "ti,sysc-omap4", "ti,sysc";
 254                         reg = <0x49900000 0x4>,
 255                               <0x49900010 0x4>;
 256                         reg-names = "rev", "sysc";
 257                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 258                         ti,sysc-midle = <SYSC_IDLE_FORCE>;
 259                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 260                                         <SYSC_IDLE_SMART>;
 261                         clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
 262                         clock-names = "fck";
 263                         #address-cells = <1>;
 264                         #size-cells = <1>;
 265                         ranges = <0x0 0x49900000 0x100000>;
 266
 267                         edma_tptc1: dma@0 {
 268                                 compatible = "ti,edma3-tptc";
 269                                 reg = <0 0x100000>;
 270                                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 271                                 interrupt-names = "edma3_tcerrint";
 272                         };
 273                 };
 274
 275                 target-module@49a00000 {
 276                         compatible = "ti,sysc-omap4", "ti,sysc";
 277                         reg = <0x49a00000 0x4>,
 278                               <0x49a00010 0x4>;
 279                         reg-names = "rev", "sysc";
 280                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 281                         ti,sysc-midle = <SYSC_IDLE_FORCE>;
 282                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 283                                         <SYSC_IDLE_SMART>;
 284                         clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
 285                         clock-names = "fck";
 286                         #address-cells = <1>;
 287                         #size-cells = <1>;
 288                         ranges = <0x0 0x49a00000 0x100000>;
 289
 290                         edma_tptc2: dma@0 {
 291                                 compatible = "ti,edma3-tptc";
 292                                 reg = <0 0x100000>;
 293                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 294                                 interrupt-names = "edma3_tcerrint";
 295                         };
 296                 };
 297
 298                 target-module@47810000 {
 299                         compatible = "ti,sysc-omap2", "ti,sysc";
 300                         reg = <0x478102fc 0x4>,
 301                               <0x47810110 0x4>,
 302                               <0x47810114 0x4>;
 303                         reg-names = "rev", "sysc", "syss";
 304                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 305                                          SYSC_OMAP2_ENAWAKEUP |
 306                                          SYSC_OMAP2_SOFTRESET |
 307                                          SYSC_OMAP2_AUTOIDLE)>;
 308                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 309                                         <SYSC_IDLE_NO>,
 310                                         <SYSC_IDLE_SMART>;
 311                         ti,syss-mask = <1>;
 312                         clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
 313                         clock-names = "fck";
 314                         #address-cells = <1>;
 315                         #size-cells = <1>;
 316                         ranges = <0x0 0x47810000 0x1000>;
 317
 318                         mmc3: mmc@0 {
 319                                 compatible = "ti,am437-sdhci";
 320                                 ti,needs-special-reset;
 321                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 322                                 reg = <0x0 0x1000>;
 323                                 status = "disabled";
 324                         };
 325                 };
 326
 327                 sham_target: target-module@53100000 {
 328                         compatible = "ti,sysc-omap3-sham", "ti,sysc";
 329                         reg = <0x53100100 0x4>,
 330                               <0x53100110 0x4>,
 331                               <0x53100114 0x4>;
 332                         reg-names = "rev", "sysc", "syss";
 333                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 334                                          SYSC_OMAP2_AUTOIDLE)>;
 335                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 336                                         <SYSC_IDLE_NO>,
 337                                         <SYSC_IDLE_SMART>;
 338                         ti,syss-mask = <1>;
 339                         /* Domains (P, C): per_pwrdm, l3_clkdm */
 340                         clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
 341                         clock-names = "fck";
 342                         #address-cells = <1>;
 343                         #size-cells = <1>;
 344                         ranges = <0x0 0x53100000 0x1000>;
 345
 346                         sham: sham@0 {
 347                                 compatible = "ti,omap5-sham";
 348                                 reg = <0 0x300>;
 349                                 dmas = <&edma 36 0>;
 350                                 dma-names = "rx";
 351                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 352                         };
 353                 };
 354
 355                 aes_target: target-module@53501000 {
 356                         compatible = "ti,sysc-omap2", "ti,sysc";
 357                         reg = <0x53501080 0x4>,
 358                               <0x53501084 0x4>,
 359                               <0x53501088 0x4>;
 360                         reg-names = "rev", "sysc", "syss";
 361                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 362                                          SYSC_OMAP2_AUTOIDLE)>;
 363                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 364                                         <SYSC_IDLE_NO>,
 365                                         <SYSC_IDLE_SMART>,
 366                                         <SYSC_IDLE_SMART_WKUP>;
 367                         ti,syss-mask = <1>;
 368                         /* Domains (P, C): per_pwrdm, l3_clkdm */
 369                         clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
 370                         clock-names = "fck";
 371                         #address-cells = <1>;
 372                         #size-cells = <1>;
 373                         ranges = <0x0 0x53501000 0x1000>;
 374
 375                         aes: aes@0 {
 376                                 compatible = "ti,omap4-aes";
 377                                 reg = <0 0xa0>;
 378                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 379                                 dmas = <&edma 6 0>,
 380                                       <&edma 5 0>;
 381                                 dma-names = "tx", "rx";
 382                         };
 383                 };
 384
 385                 des_target: target-module@53701000 {
 386                         compatible = "ti,sysc-omap2", "ti,sysc";
 387                         reg = <0x53701030 0x4>,
 388                               <0x53701034 0x4>,
 389                               <0x53701038 0x4>;
 390                         reg-names = "rev", "sysc", "syss";
 391                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 392                                          SYSC_OMAP2_AUTOIDLE)>;
 393                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 394                                         <SYSC_IDLE_NO>,
 395                                         <SYSC_IDLE_SMART>,
 396                                         <SYSC_IDLE_SMART_WKUP>;
 397                         ti,syss-mask = <1>;
 398                         /* Domains (P, C): per_pwrdm, l3_clkdm */
 399                         clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
 400                         clock-names = "fck";
 401                         #address-cells = <1>;
 402                         #size-cells = <1>;
 403                         ranges = <0 0x53701000 0x1000>;
 404
 405                         des: des@0 {
 406                                 compatible = "ti,omap4-des";
 407                                 reg = <0 0xa0>;
 408                                 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
 409                                 dmas = <&edma 34 0>,
 410                                        <&edma 33 0>;
 411                                 dma-names = "tx", "rx";
 412                         };
 413                 };
 414
 415                 pruss_tm: target-module@54400000 {
 416                         compatible = "ti,sysc-pruss", "ti,sysc";
 417                         reg = <0x54426000 0x4>,
 418                               <0x54426004 0x4>;
 419                         reg-names = "rev", "sysc";
 420                         ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
 421                                          SYSC_PRUSS_SUB_MWAIT)>;
 422                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 423                                         <SYSC_IDLE_NO>,
 424                                         <SYSC_IDLE_SMART>;
 425                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 426                                         <SYSC_IDLE_NO>,
 427                                         <SYSC_IDLE_SMART>;
 428                         clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
 429                         clock-names = "fck";
 430                         resets = <&prm_per 1>;
 431                         reset-names = "rstctrl";
 432                         #address-cells = <1>;
 433                         #size-cells = <1>;
 434                         ranges = <0x0 0x54400000 0x80000>;
 435                 };
 436
 437                 gpmc: gpmc@50000000 {
 438                         compatible = "ti,am3352-gpmc";
 439                         ti,hwmods = "gpmc";
 440                         dmas = <&edma 52 0>;
 441                         dma-names = "rxtx";
 442                         clocks = <&l3s_gclk>;
 443                         clock-names = "fck";
 444                         reg = <0x50000000 0x2000>;
 445                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 446                         gpmc,num-cs = <7>;
 447                         gpmc,num-waitpins = <2>;
 448                         #address-cells = <2>;
 449                         #size-cells = <1>;
 450                         interrupt-controller;
 451                         #interrupt-cells = <2>;
 452                         gpio-controller;
 453                         #gpio-cells = <2>;
 454                         status = "disabled";
 455                 };
 456
 457                 target-module@47900000 {
 458                         compatible = "ti,sysc-omap4", "ti,sysc";
 459                         reg = <0x47900000 0x4>,
 460                               <0x47900010 0x4>;
 461                         reg-names = "rev", "sysc";
 462                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 463                                         <SYSC_IDLE_NO>,
 464                                         <SYSC_IDLE_SMART>,
 465                                         <SYSC_IDLE_SMART_WKUP>;
 466                         clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
 467                         clock-names = "fck";
 468                         #address-cells = <1>;
 469                         #size-cells = <1>;
 470                         ranges = <0x0 0x47900000 0x1000>,
 471                                  <0x30000000 0x30000000 0x4000000>;
 472
 473                         qspi: spi@0 {
 474                                 compatible = "ti,am4372-qspi";
 475                                 reg = <0 0x100>,
 476                                       <0x30000000 0x4000000>;
 477                                 reg-names = "qspi_base", "qspi_mmap";
 478                                 clocks = <&dpll_per_m2_div4_ck>;
 479                                 clock-names = "fck";
 480                                 #address-cells = <1>;
 481                                 #size-cells = <0>;
 482                                 interrupts = <0 138 0x4>;
 483                                 num-cs = <4>;
 484                         };
 485                 };
 486
 487                 ocmcram: sram@40300000 {
 488                         compatible = "mmio-sram";
 489                         reg = <0x40300000 0x40000>; /* 256k */
 490                         ranges = <0x0 0x40300000 0x40000>;
 491                         #address-cells = <1>;
 492                         #size-cells = <1>;
 493
 494                         pm_sram_code: pm-code-sram@0 {
 495                                 compatible = "ti,sram";
 496                                 reg = <0x0 0x1000>;
 497                                 protect-exec;
 498                         };
 499
 500                         pm_sram_data: pm-data-sram@1000 {
 501                                 compatible = "ti,sram";
 502                                 reg = <0x1000 0x1000>;
 503                                 pool;
 504                         };
 505                 };
 506
 507                 target-module@56000000 {
 508                         compatible = "ti,sysc-omap4", "ti,sysc";
 509                         reg = <0x5600fe00 0x4>,
 510                               <0x5600fe10 0x4>;
 511                         reg-names = "rev", "sysc";
 512                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 513                                         <SYSC_IDLE_NO>,
 514                                         <SYSC_IDLE_SMART>;
 515                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 516                                         <SYSC_IDLE_NO>,
 517                                         <SYSC_IDLE_SMART>;
 518                         clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
 519                         clock-names = "fck";
 520                         power-domains = <&prm_gfx>;
 521                         resets = <&prm_gfx 0>;
 522                         reset-names = "rstctrl";
 523                         #address-cells = <1>;
 524                         #size-cells = <1>;
 525                         ranges = <0 0x56000000 0x1000000>;
 526                 };
 527         };
 528 };
 529
 530 #include "am437x-l4.dtsi"
 531 #include "am43xx-clocks.dtsi"
 532
 533 &prcm {
 534         prm_gfx: prm@400 {
 535                 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
 536                 reg = <0x400 0x100>;
 537                 #power-domain-cells = <0>;
 538                 #reset-cells = <1>;
 539         };
 540
 541         prm_per: prm@800 {
 542                 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
 543                 reg = <0x800 0x100>;
 544                 #reset-cells = <1>;
 545         };
 546
 547         prm_wkup: prm@2000 {
 548                 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
 549                 reg = <0x2000 0x100>;
 550                 #reset-cells = <1>;
 551         };
 552
 553         prm_device: prm@4000 {
 554                 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
 555                 reg = <0x4000 0x100>;
 556                 #reset-cells = <1>;
 557         };
 558 };
 559
 560 /* Preferred always-on timer for clocksource */
 561 &timer1_target {
 562         ti,no-reset-on-init;
 563         ti,no-idle;
 564         timer@0 {
 565                 assigned-clocks = <&timer1_fck>;
 566                 assigned-clock-parents = <&sys_clkin_ck>;
 567         };
 568 };
 569
 570 /* Preferred timer for clockevent */
 571 &timer2_target {
 572         ti,no-reset-on-init;
 573         ti,no-idle;
 574         timer@0 {
 575                 assigned-clocks = <&timer2_fck>;
 576                 assigned-clock-parents = <&sys_clkin_ck>;
 577         };
 578 };