arch/arm/boot/dts/am335x-chilisom.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/
   4  * Author: Rostislav Lisovy <lisovy@jablotron.cz>
   5  */
   6 #include "am33xx.dtsi"
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8
   9 / {
  10         model = "Grinn AM335x ChiliSOM";
  11         compatible = "grinn,am335x-chilisom", "ti,am33xx";
  12
  13         cpus {
  14                 cpu@0 {
  15                         cpu0-supply = <&dcdc2_reg>;
  16                 };
  17         };
  18
  19         memory@80000000 {
  20                 device_type = "memory";
  21                 reg = <0x80000000 0x20000000>; /* 512 MB */
  22         };
  23 };
  24
  25 &am33xx_pinmux {
  26         pinctrl-names = "default";
  27
  28         i2c0_pins: pinmux_i2c0_pins {
  29                 pinctrl-single,pins = <
  30                         AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
  31                         AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
  32                 >;
  33         };
  34
  35         nandflash_pins: nandflash_pins {
  36                 pinctrl-single,pins = <
  37                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
  38                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
  39                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE0)
  40                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE0)
  41                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE0)
  42                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE0)
  43                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE0)
  44                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE0)
  45
  46                         AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
  47                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE0)
  48                         AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT_PULLUP, MUX_MODE0)
  49                         AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT_PULLUP, MUX_MODE0)
  50                         AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT_PULLUP, MUX_MODE0)
  51                         AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT_PULLUP, MUX_MODE0)
  52                 >;
  53         };
  54 };
  55
  56 &i2c0 {
  57         pinctrl-names = "default";
  58         pinctrl-0 = <&i2c0_pins>;
  59
  60         status = "okay";
  61         clock-frequency = <400000>;
  62
  63         tps: tps@24 {
  64                 reg = <0x24>;
  65         };
  66
  67 };
  68
  69 /include/ "tps65217.dtsi"
  70
  71 &tps {
  72         regulators {
  73                 dcdc1_reg: regulator@0 {
  74                         regulator-name = "vdds_dpr";
  75                         regulator-always-on;
  76                 };
  77
  78                 dcdc2_reg: regulator@1 {
  79                         /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
  80                         regulator-name = "vdd_mpu";
  81                         regulator-min-microvolt = <925000>;
  82                         regulator-max-microvolt = <1325000>;
  83                         regulator-boot-on;
  84                         regulator-always-on;
  85                 };
  86
  87                 dcdc3_reg: regulator@2 {
  88                         /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
  89                         regulator-name = "vdd_core";
  90                         regulator-min-microvolt = <925000>;
  91                         regulator-max-microvolt = <1150000>;
  92                         regulator-boot-on;
  93                         regulator-always-on;
  94                 };
  95
  96                 ldo1_reg: regulator@3 {
  97                         regulator-name = "vio,vrtc,vdds";
  98                         regulator-boot-on;
  99                         regulator-always-on;
 100                 };
 101
 102                 ldo2_reg: regulator@4 {
 103                         regulator-name = "vdd_3v3aux";
 104                         regulator-boot-on;
 105                         regulator-always-on;
 106                 };
 107
 108                 ldo3_reg: regulator@5 {
 109                         regulator-name = "vdd_1v8";
 110                         regulator-boot-on;
 111                         regulator-always-on;
 112                 };
 113
 114                 ldo4_reg: regulator@6 {
 115                         regulator-name = "vdd_3v3d";
 116                         regulator-boot-on;
 117                         regulator-always-on;
 118                 };
 119         };
 120 };
 121
 122 &rtc {
 123         system-power-controller;
 124
 125         pinctrl-0 = <&ext_wakeup>;
 126         pinctrl-names = "default";
 127
 128         ext_wakeup: ext-wakeup {
 129                 pins = "ext_wakeup0";
 130                 input-enable;
 131         };
 132 };
 133
 134 /* NAND Flash */
 135 &elm {
 136         status = "okay";
 137 };
 138
 139 &gpmc {
 140         status = "okay";
 141         pinctrl-names = "default";
 142         pinctrl-0 = <&nandflash_pins>;
 143         ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
 144         nand@0,0 {
 145                 compatible = "ti,omap2-nand";
 146                 reg = <0 0 4>;  /* CS0, offset 0, IO size 4 */
 147                 interrupt-parent = <&gpmc>;
 148                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 149                              <1 IRQ_TYPE_NONE>; /* termcount */
 150                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
 151                 ti,nand-ecc-opt = "bch8";
 152                 ti,elm-id = <&elm>;
 153                 nand-bus-width = <8>;
 154                 gpmc,device-width = <1>;
 155                 gpmc,sync-clk-ps = <0>;
 156                 gpmc,cs-on-ns = <0>;
 157                 gpmc,cs-rd-off-ns = <44>;
 158                 gpmc,cs-wr-off-ns = <44>;
 159                 gpmc,adv-on-ns = <6>;
 160                 gpmc,adv-rd-off-ns = <34>;
 161                 gpmc,adv-wr-off-ns = <44>;
 162                 gpmc,we-on-ns = <0>;
 163                 gpmc,we-off-ns = <40>;
 164                 gpmc,oe-on-ns = <0>;
 165                 gpmc,oe-off-ns = <54>;
 166                 gpmc,access-ns = <64>;
 167                 gpmc,rd-cycle-ns = <82>;
 168                 gpmc,wr-cycle-ns = <82>;
 169                 gpmc,bus-turnaround-ns = <0>;
 170                 gpmc,cycle2cycle-delay-ns = <0>;
 171                 gpmc,clk-activation-ns = <0>;
 172                 gpmc,wr-access-ns = <40>;
 173                 gpmc,wr-data-mux-bus-ns = <0>;
 174         };
 175 };