1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_CLOCKSOURCE_DATA
6 select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DEVMEM_IS_ALLOWED
9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_FORTIFY_SOURCE
12 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
13 select ARCH_HAS_PHYS_TO_DMA
14 select ARCH_HAS_SET_MEMORY
15 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
16 select ARCH_HAS_STRICT_MODULE_RWX if MMU
17 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
18 select ARCH_HAVE_CUSTOM_GPIO_H
19 select ARCH_HAS_GCOV_PROFILE_ALL
20 select ARCH_MIGHT_HAVE_PC_PARPORT
21 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
22 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
23 select ARCH_SUPPORTS_ATOMIC_RMW
24 select ARCH_USE_BUILTIN_BSWAP
25 select ARCH_USE_CMPXCHG_LOCKREF
26 select ARCH_WANT_IPC_PARSE_VERSION
27 select BUILDTIME_EXTABLE_SORT if MMU
28 select CLONE_BACKWARDS
29 select CPU_PM if (SUSPEND || CPU_IDLE)
30 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
31 select DMA_DIRECT_OPS if !MMU
33 select EDAC_ATOMIC_SCRUB
34 select GENERIC_ALLOCATOR
35 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
36 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
37 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
38 select GENERIC_CPU_AUTOPROBE
39 select GENERIC_EARLY_IOREMAP
40 select GENERIC_IDLE_POLL_SETUP
41 select GENERIC_IRQ_PROBE
42 select GENERIC_IRQ_SHOW
43 select GENERIC_IRQ_SHOW_LEVEL
44 select GENERIC_PCI_IOMAP
45 select GENERIC_SCHED_CLOCK
46 select GENERIC_SMP_IDLE_THREAD
47 select GENERIC_STRNCPY_FROM_USER
48 select GENERIC_STRNLEN_USER
49 select HANDLE_DOMAIN_IRQ
50 select HARDIRQS_SW_RESEND
51 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
52 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
53 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
54 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
55 select HAVE_ARCH_MMAP_RND_BITS if MMU
56 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
57 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
58 select HAVE_ARCH_TRACEHOOK
59 select HAVE_ARM_SMCCC if CPU_V7
60 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
61 select HAVE_CONTEXT_TRACKING
62 select HAVE_C_RECORDMCOUNT
63 select HAVE_DEBUG_KMEMLEAK
64 select HAVE_DMA_CONTIGUOUS if MMU
65 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
66 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
67 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
68 select HAVE_EXIT_THREAD
69 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
70 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
71 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
72 select HAVE_GCC_PLUGINS
73 select HAVE_GENERIC_DMA_COHERENT
74 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
75 select HAVE_IDE if PCI || ISA || PCMCIA
76 select HAVE_IRQ_TIME_ACCOUNTING
77 select HAVE_KERNEL_GZIP
78 select HAVE_KERNEL_LZ4
79 select HAVE_KERNEL_LZMA
80 select HAVE_KERNEL_LZO
82 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
83 select HAVE_KRETPROBES if (HAVE_KPROBES)
85 select HAVE_MOD_ARCH_SPECIFIC
87 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
88 select HAVE_OPTPROBES if !THUMB2_KERNEL
89 select HAVE_PERF_EVENTS
91 select HAVE_PERF_USER_STACK_DUMP
92 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
93 select HAVE_REGS_AND_STACK_ACCESS_API
95 select HAVE_STACKPROTECTOR
96 select HAVE_SYSCALL_TRACEPOINTS
98 select HAVE_VIRT_CPU_ACCOUNTING_GEN
99 select IRQ_FORCED_THREADING
100 select MODULES_USE_ELF_REL
101 select NEED_DMA_MAP_STATE
103 select OF_EARLY_FLATTREE if OF
104 select OF_RESERVED_MEM if OF
106 select OLD_SIGSUSPEND3
107 select PERF_USE_VMALLOC
110 select SYS_SUPPORTS_APM_EMULATION
111 # Above selects are sorted alphabetically; please add new ones
112 # according to that. Thanks.
114 The ARM series is a line of low-power-consumption RISC chip designs
115 licensed by ARM Ltd and targeted at embedded applications and
116 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
117 manufactured, but legacy ARM-based PC hardware remains popular in
118 Europe. There is an ARM Linux project with a web page at
119 <http://www.arm.linux.org.uk/>.
121 config ARM_HAS_SG_CHAIN
122 select ARCH_HAS_SG_CHAIN
125 config ARM_DMA_USE_IOMMU
127 select ARM_HAS_SG_CHAIN
128 select NEED_SG_DMA_LENGTH
132 config ARM_DMA_IOMMU_ALIGNMENT
133 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
137 DMA mapping framework by default aligns all buffers to the smallest
138 PAGE_SIZE order which is greater than or equal to the requested buffer
139 size. This works well for buffers up to a few hundreds kilobytes, but
140 for larger buffers it just a waste of address space. Drivers which has
141 relatively small addressing window (like 64Mib) might run out of
142 virtual space with just a few allocations.
144 With this parameter you can specify the maximum PAGE_SIZE order for
145 DMA IOMMU buffers. Larger buffers will be aligned only to this
146 specified order. The order is expressed as a power of two multiplied
151 config MIGHT_HAVE_PCI
154 config SYS_SUPPORTS_APM_EMULATION
159 select GENERIC_ALLOCATOR
170 The Extended Industry Standard Architecture (EISA) bus was
171 developed as an open alternative to the IBM MicroChannel bus.
173 The EISA bus provided some of the features of the IBM MicroChannel
174 bus while maintaining backward compatibility with cards made for
175 the older ISA bus. The EISA bus saw limited use between 1988 and
176 1995 when it was made obsolete by the PCI bus.
178 Say Y here if you are building a kernel for an EISA-based machine.
185 config STACKTRACE_SUPPORT
189 config LOCKDEP_SUPPORT
193 config TRACE_IRQFLAGS_SUPPORT
197 config RWSEM_XCHGADD_ALGORITHM
201 config ARCH_HAS_ILOG2_U32
204 config ARCH_HAS_ILOG2_U64
207 config ARCH_HAS_BANDGAP
210 config FIX_EARLYCON_MEM
213 config GENERIC_HWEIGHT
217 config GENERIC_CALIBRATE_DELAY
221 config ARCH_MAY_HAVE_PC_FDC
227 config ARCH_SUPPORTS_UPROBES
230 config ARCH_HAS_DMA_SET_COHERENT_MASK
233 config GENERIC_ISA_DMA
239 config NEED_RET_TO_USER
245 config ARM_PATCH_PHYS_VIRT
246 bool "Patch physical to virtual translations at runtime" if EMBEDDED
248 depends on !XIP_KERNEL && MMU
250 Patch phys-to-virt and virt-to-phys translation functions at
251 boot and module load time according to the position of the
252 kernel in system memory.
254 This can only be used with non-XIP MMU kernels where the base
255 of physical memory is at a 16MB boundary.
257 Only disable this option if you know that you do not require
258 this feature (eg, building a kernel for a single machine) and
259 you need to shrink the kernel to the minimal size.
261 config NEED_MACH_IO_H
264 Select this when mach/io.h is required to provide special
265 definitions for this platform. The need for mach/io.h should
266 be avoided when possible.
268 config NEED_MACH_MEMORY_H
271 Select this when mach/memory.h is required to provide special
272 definitions for this platform. The need for mach/memory.h should
273 be avoided when possible.
276 hex "Physical address of main memory" if MMU
277 depends on !ARM_PATCH_PHYS_VIRT
278 default DRAM_BASE if !MMU
279 default 0x00000000 if ARCH_EBSA110 || \
285 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
286 default 0x20000000 if ARCH_S5PV210
287 default 0xc0000000 if ARCH_SA1100
289 Please provide the physical address corresponding to the
290 location of main memory in your system.
296 config PGTABLE_LEVELS
298 default 3 if ARM_LPAE
301 source "init/Kconfig"
303 source "kernel/Kconfig.freezer"
308 bool "MMU-based Paged Memory Management Support"
311 Select if you want MMU-based virtualised addressing space
312 support by paged memory management. If unsure, say 'Y'.
314 config ARCH_MMAP_RND_BITS_MIN
317 config ARCH_MMAP_RND_BITS_MAX
318 default 14 if PAGE_OFFSET=0x40000000
319 default 15 if PAGE_OFFSET=0x80000000
323 # The "ARM system type" choice list is ordered alphabetically by option
324 # text. Please add new entries in the option alphabetic order.
327 prompt "ARM system type"
328 default ARM_SINGLE_ARMV7M if !MMU
329 default ARCH_MULTIPLATFORM if MMU
331 config ARCH_MULTIPLATFORM
332 bool "Allow multiple platforms to be selected"
334 select ARM_HAS_SG_CHAIN
335 select ARM_PATCH_PHYS_VIRT
339 select GENERIC_CLOCKEVENTS
340 select GENERIC_IRQ_MULTI_HANDLER
341 select MIGHT_HAVE_PCI
342 select PCI_DOMAINS if PCI
346 config ARM_SINGLE_ARMV7M
347 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
354 select GENERIC_CLOCKEVENTS
361 select ARCH_USES_GETTIMEOFFSET
364 select NEED_MACH_IO_H
365 select NEED_MACH_MEMORY_H
368 This is an evaluation board for the StrongARM processor available
369 from Digital. It has limited hardware on-board, including an
370 Ethernet interface, two PCMCIA sockets, two serial ports and a
375 select ARCH_SPARSEMEM_ENABLE
377 imply ARM_PATCH_PHYS_VIRT
383 select GENERIC_CLOCKEVENTS
386 This enables support for the Cirrus EP93xx series of CPUs.
388 config ARCH_FOOTBRIDGE
392 select GENERIC_CLOCKEVENTS
394 select NEED_MACH_IO_H if !MMU
395 select NEED_MACH_MEMORY_H
397 Support for systems based on the DC21285 companion chip
398 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
401 bool "Hilscher NetX based"
405 select GENERIC_CLOCKEVENTS
407 This enables support for systems based on the Hilscher NetX Soc
413 select NEED_MACH_MEMORY_H
414 select NEED_RET_TO_USER
420 Support for Intel's IOP13XX (XScale) family of processors.
428 select NEED_RET_TO_USER
432 Support for Intel's 80219 and IOP32X (XScale) family of
441 select NEED_RET_TO_USER
445 Support for Intel's IOP33X (XScale) family of processors.
450 select ARCH_HAS_DMA_SET_COHERENT_MASK
451 select ARCH_SUPPORTS_BIG_ENDIAN
454 select DMABOUNCE if PCI
455 select GENERIC_CLOCKEVENTS
457 select MIGHT_HAVE_PCI
458 select NEED_MACH_IO_H
459 select USB_EHCI_BIG_ENDIAN_DESC
460 select USB_EHCI_BIG_ENDIAN_MMIO
462 Support for Intel's IXP4XX (XScale) family of processors.
467 select GENERIC_CLOCKEVENTS
468 select GENERIC_IRQ_MULTI_HANDLER
470 select MIGHT_HAVE_PCI
474 select PLAT_ORION_LEGACY
476 select PM_GENERIC_DOMAINS if PM
478 Support for the Marvell Dove SoC 88AP510
481 bool "Micrel/Kendin KS8695"
484 select GENERIC_CLOCKEVENTS
486 select NEED_MACH_MEMORY_H
488 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
489 System-on-Chip devices.
492 bool "Nuvoton W90X900 CPU"
496 select GENERIC_CLOCKEVENTS
499 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
500 At present, the w90x900 has been renamed nuc900, regarding
501 the ARM series product line, you can login the following
502 link address to know more.
504 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
505 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
511 select CLKSRC_LPC32XX
514 select GENERIC_CLOCKEVENTS
515 select GENERIC_IRQ_MULTI_HANDLER
520 Support for the NXP LPC32XX family of processors
523 bool "PXA2xx/PXA3xx-based"
526 select ARM_CPU_SUSPEND if PM
533 select CPU_XSCALE if !CPU_XSC3
534 select GENERIC_CLOCKEVENTS
535 select GENERIC_IRQ_MULTI_HANDLER
543 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
549 select ARCH_MAY_HAVE_PC_FDC
550 select ARCH_SPARSEMEM_ENABLE
551 select ARCH_USES_GETTIMEOFFSET
555 select HAVE_PATA_PLATFORM
557 select NEED_MACH_IO_H
558 select NEED_MACH_MEMORY_H
561 On the Acorn Risc-PC, Linux can support the internal IDE disk and
562 CD-ROM interface, serial and parallel port, and the floppy drive.
567 select ARCH_SPARSEMEM_ENABLE
571 select TIMER_OF if OF
574 select GENERIC_CLOCKEVENTS
575 select GENERIC_IRQ_MULTI_HANDLER
580 select NEED_MACH_MEMORY_H
583 Support for StrongARM 11x0 based boards.
586 bool "Samsung S3C24XX SoCs"
589 select CLKSRC_SAMSUNG_PWM
590 select GENERIC_CLOCKEVENTS
593 select GENERIC_IRQ_MULTI_HANDLER
594 select HAVE_S3C2410_I2C if I2C
595 select HAVE_S3C2410_WATCHDOG if WATCHDOG
596 select HAVE_S3C_RTC if RTC_CLASS
597 select NEED_MACH_IO_H
601 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
602 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
603 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
604 Samsung SMDK2410 development board (and derivatives).
608 select ARCH_HAS_HOLES_MEMORYMODEL
611 select GENERIC_ALLOCATOR
612 select GENERIC_CLOCKEVENTS
613 select GENERIC_IRQ_CHIP
619 Support for TI's DaVinci platform.
624 select ARCH_HAS_HOLES_MEMORYMODEL
628 select GENERIC_CLOCKEVENTS
629 select GENERIC_IRQ_CHIP
630 select GENERIC_IRQ_MULTI_HANDLER
634 select NEED_MACH_IO_H if PCCARD
635 select NEED_MACH_MEMORY_H
638 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
642 menu "Multiple platform selection"
643 depends on ARCH_MULTIPLATFORM
645 comment "CPU Core family selection"
648 bool "ARMv4 based platforms (FA526)"
649 depends on !ARCH_MULTI_V6_V7
650 select ARCH_MULTI_V4_V5
653 config ARCH_MULTI_V4T
654 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
655 depends on !ARCH_MULTI_V6_V7
656 select ARCH_MULTI_V4_V5
657 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
658 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
659 CPU_ARM925T || CPU_ARM940T)
662 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
663 depends on !ARCH_MULTI_V6_V7
664 select ARCH_MULTI_V4_V5
665 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
666 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
667 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
669 config ARCH_MULTI_V4_V5
673 bool "ARMv6 based platforms (ARM11)"
674 select ARCH_MULTI_V6_V7
678 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
680 select ARCH_MULTI_V6_V7
684 config ARCH_MULTI_V6_V7
686 select MIGHT_HAVE_CACHE_L2X0
688 config ARCH_MULTI_CPU_AUTO
689 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
695 bool "Dummy Virtual Machine"
696 depends on ARCH_MULTI_V7
699 select ARM_GIC_V2M if PCI
701 select ARM_GIC_V3_ITS if PCI
703 select HAVE_ARM_ARCH_TIMER
706 # This is sorted alphabetically by mach-* pathname. However, plat-*
707 # Kconfigs may be included either alphabetically (according to the
708 # plat- suffix) or along side the corresponding mach-* source.
710 source "arch/arm/mach-actions/Kconfig"
712 source "arch/arm/mach-alpine/Kconfig"
714 source "arch/arm/mach-artpec/Kconfig"
716 source "arch/arm/mach-asm9260/Kconfig"
718 source "arch/arm/mach-aspeed/Kconfig"
720 source "arch/arm/mach-at91/Kconfig"
722 source "arch/arm/mach-axxia/Kconfig"
724 source "arch/arm/mach-bcm/Kconfig"
726 source "arch/arm/mach-berlin/Kconfig"
728 source "arch/arm/mach-clps711x/Kconfig"
730 source "arch/arm/mach-cns3xxx/Kconfig"
732 source "arch/arm/mach-davinci/Kconfig"
734 source "arch/arm/mach-digicolor/Kconfig"
736 source "arch/arm/mach-dove/Kconfig"
738 source "arch/arm/mach-ep93xx/Kconfig"
740 source "arch/arm/mach-exynos/Kconfig"
741 source "arch/arm/plat-samsung/Kconfig"
743 source "arch/arm/mach-footbridge/Kconfig"
745 source "arch/arm/mach-gemini/Kconfig"
747 source "arch/arm/mach-highbank/Kconfig"
749 source "arch/arm/mach-hisi/Kconfig"
751 source "arch/arm/mach-imx/Kconfig"
753 source "arch/arm/mach-integrator/Kconfig"
755 source "arch/arm/mach-iop13xx/Kconfig"
757 source "arch/arm/mach-iop32x/Kconfig"
759 source "arch/arm/mach-iop33x/Kconfig"
761 source "arch/arm/mach-ixp4xx/Kconfig"
763 source "arch/arm/mach-keystone/Kconfig"
765 source "arch/arm/mach-ks8695/Kconfig"
767 source "arch/arm/mach-mediatek/Kconfig"
769 source "arch/arm/mach-meson/Kconfig"
771 source "arch/arm/mach-mmp/Kconfig"
773 source "arch/arm/mach-moxart/Kconfig"
775 source "arch/arm/mach-mv78xx0/Kconfig"
777 source "arch/arm/mach-mvebu/Kconfig"
779 source "arch/arm/mach-mxs/Kconfig"
781 source "arch/arm/mach-netx/Kconfig"
783 source "arch/arm/mach-nomadik/Kconfig"
785 source "arch/arm/mach-npcm/Kconfig"
787 source "arch/arm/mach-nspire/Kconfig"
789 source "arch/arm/plat-omap/Kconfig"
791 source "arch/arm/mach-omap1/Kconfig"
793 source "arch/arm/mach-omap2/Kconfig"
795 source "arch/arm/mach-orion5x/Kconfig"
797 source "arch/arm/mach-oxnas/Kconfig"
799 source "arch/arm/mach-picoxcell/Kconfig"
801 source "arch/arm/mach-prima2/Kconfig"
803 source "arch/arm/mach-pxa/Kconfig"
804 source "arch/arm/plat-pxa/Kconfig"
806 source "arch/arm/mach-qcom/Kconfig"
808 source "arch/arm/mach-realview/Kconfig"
810 source "arch/arm/mach-rockchip/Kconfig"
812 source "arch/arm/mach-s3c24xx/Kconfig"
814 source "arch/arm/mach-s3c64xx/Kconfig"
816 source "arch/arm/mach-s5pv210/Kconfig"
818 source "arch/arm/mach-sa1100/Kconfig"
820 source "arch/arm/mach-shmobile/Kconfig"
822 source "arch/arm/mach-socfpga/Kconfig"
824 source "arch/arm/mach-spear/Kconfig"
826 source "arch/arm/mach-sti/Kconfig"
828 source "arch/arm/mach-stm32/Kconfig"
830 source "arch/arm/mach-sunxi/Kconfig"
832 source "arch/arm/mach-tango/Kconfig"
834 source "arch/arm/mach-tegra/Kconfig"
836 source "arch/arm/mach-u300/Kconfig"
838 source "arch/arm/mach-uniphier/Kconfig"
840 source "arch/arm/mach-ux500/Kconfig"
842 source "arch/arm/mach-versatile/Kconfig"
844 source "arch/arm/mach-vexpress/Kconfig"
845 source "arch/arm/plat-versatile/Kconfig"
847 source "arch/arm/mach-vt8500/Kconfig"
849 source "arch/arm/mach-w90x900/Kconfig"
851 source "arch/arm/mach-zx/Kconfig"
853 source "arch/arm/mach-zynq/Kconfig"
855 # ARMv7-M architecture
857 bool "Energy Micro efm32"
858 depends on ARM_SINGLE_ARMV7M
861 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
865 bool "NXP LPC18xx/LPC43xx"
866 depends on ARM_SINGLE_ARMV7M
867 select ARCH_HAS_RESET_CONTROLLER
869 select CLKSRC_LPC32XX
872 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
873 high performance microcontrollers.
876 bool "ARM MPS2 platform"
877 depends on ARM_SINGLE_ARMV7M
881 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
882 with a range of available cores like Cortex-M3/M4/M7.
884 Please, note that depends which Application Note is used memory map
885 for the platform may vary, so adjustment of RAM base might be needed.
887 # Definitions to make life easier
893 select GENERIC_CLOCKEVENTS
899 select GENERIC_IRQ_CHIP
902 config PLAT_ORION_LEGACY
909 config PLAT_VERSATILE
912 source "arch/arm/firmware/Kconfig"
914 source arch/arm/mm/Kconfig
917 bool "Enable iWMMXt support"
918 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
919 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
921 Enable support for iWMMXt context switching at run time if
922 running on a CPU that supports it.
925 source "arch/arm/Kconfig-nommu"
928 config PJ4B_ERRATA_4742
929 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
930 depends on CPU_PJ4B && MACH_ARMADA_370
933 When coming out of either a Wait for Interrupt (WFI) or a Wait for
934 Event (WFE) IDLE states, a specific timing sensitivity exists between
935 the retiring WFI/WFE instructions and the newly issued subsequent
936 instructions. This sensitivity can result in a CPU hang scenario.
938 The software must insert either a Data Synchronization Barrier (DSB)
939 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
942 config ARM_ERRATA_326103
943 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
946 Executing a SWP instruction to read-only memory does not set bit 11
947 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
948 treat the access as a read, preventing a COW from occurring and
949 causing the faulting task to livelock.
951 config ARM_ERRATA_411920
952 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
953 depends on CPU_V6 || CPU_V6K
955 Invalidation of the Instruction Cache operation can
956 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
957 It does not affect the MPCore. This option enables the ARM Ltd.
958 recommended workaround.
960 config ARM_ERRATA_430973
961 bool "ARM errata: Stale prediction on replaced interworking branch"
964 This option enables the workaround for the 430973 Cortex-A8
965 r1p* erratum. If a code sequence containing an ARM/Thumb
966 interworking branch is replaced with another code sequence at the
967 same virtual address, whether due to self-modifying code or virtual
968 to physical address re-mapping, Cortex-A8 does not recover from the
969 stale interworking branch prediction. This results in Cortex-A8
970 executing the new code sequence in the incorrect ARM or Thumb state.
971 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
972 and also flushes the branch target cache at every context switch.
973 Note that setting specific bits in the ACTLR register may not be
974 available in non-secure mode.
976 config ARM_ERRATA_458693
977 bool "ARM errata: Processor deadlock when a false hazard is created"
979 depends on !ARCH_MULTIPLATFORM
981 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
982 erratum. For very specific sequences of memory operations, it is
983 possible for a hazard condition intended for a cache line to instead
984 be incorrectly associated with a different cache line. This false
985 hazard might then cause a processor deadlock. The workaround enables
986 the L1 caching of the NEON accesses and disables the PLD instruction
987 in the ACTLR register. Note that setting specific bits in the ACTLR
988 register may not be available in non-secure mode.
990 config ARM_ERRATA_460075
991 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
993 depends on !ARCH_MULTIPLATFORM
995 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
996 erratum. Any asynchronous access to the L2 cache may encounter a
997 situation in which recent store transactions to the L2 cache are lost
998 and overwritten with stale memory contents from external memory. The
999 workaround disables the write-allocate mode for the L2 cache via the
1000 ACTLR register. Note that setting specific bits in the ACTLR register
1001 may not be available in non-secure mode.
1003 config ARM_ERRATA_742230
1004 bool "ARM errata: DMB operation may be faulty"
1005 depends on CPU_V7 && SMP
1006 depends on !ARCH_MULTIPLATFORM
1008 This option enables the workaround for the 742230 Cortex-A9
1009 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1010 between two write operations may not ensure the correct visibility
1011 ordering of the two writes. This workaround sets a specific bit in
1012 the diagnostic register of the Cortex-A9 which causes the DMB
1013 instruction to behave as a DSB, ensuring the correct behaviour of
1016 config ARM_ERRATA_742231
1017 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1018 depends on CPU_V7 && SMP
1019 depends on !ARCH_MULTIPLATFORM
1021 This option enables the workaround for the 742231 Cortex-A9
1022 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1023 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1024 accessing some data located in the same cache line, may get corrupted
1025 data due to bad handling of the address hazard when the line gets
1026 replaced from one of the CPUs at the same time as another CPU is
1027 accessing it. This workaround sets specific bits in the diagnostic
1028 register of the Cortex-A9 which reduces the linefill issuing
1029 capabilities of the processor.
1031 config ARM_ERRATA_643719
1032 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1033 depends on CPU_V7 && SMP
1036 This option enables the workaround for the 643719 Cortex-A9 (prior to
1037 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1038 register returns zero when it should return one. The workaround
1039 corrects this value, ensuring cache maintenance operations which use
1040 it behave as intended and avoiding data corruption.
1042 config ARM_ERRATA_720789
1043 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1046 This option enables the workaround for the 720789 Cortex-A9 (prior to
1047 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1048 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1049 As a consequence of this erratum, some TLB entries which should be
1050 invalidated are not, resulting in an incoherency in the system page
1051 tables. The workaround changes the TLB flushing routines to invalidate
1052 entries regardless of the ASID.
1054 config ARM_ERRATA_743622
1055 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1057 depends on !ARCH_MULTIPLATFORM
1059 This option enables the workaround for the 743622 Cortex-A9
1060 (r2p*) erratum. Under very rare conditions, a faulty
1061 optimisation in the Cortex-A9 Store Buffer may lead to data
1062 corruption. This workaround sets a specific bit in the diagnostic
1063 register of the Cortex-A9 which disables the Store Buffer
1064 optimisation, preventing the defect from occurring. This has no
1065 visible impact on the overall performance or power consumption of the
1068 config ARM_ERRATA_751472
1069 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1071 depends on !ARCH_MULTIPLATFORM
1073 This option enables the workaround for the 751472 Cortex-A9 (prior
1074 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1075 completion of a following broadcasted operation if the second
1076 operation is received by a CPU before the ICIALLUIS has completed,
1077 potentially leading to corrupted entries in the cache or TLB.
1079 config ARM_ERRATA_754322
1080 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1083 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1084 r3p*) erratum. A speculative memory access may cause a page table walk
1085 which starts prior to an ASID switch but completes afterwards. This
1086 can populate the micro-TLB with a stale entry which may be hit with
1087 the new ASID. This workaround places two dsb instructions in the mm
1088 switching code so that no page table walks can cross the ASID switch.
1090 config ARM_ERRATA_754327
1091 bool "ARM errata: no automatic Store Buffer drain"
1092 depends on CPU_V7 && SMP
1094 This option enables the workaround for the 754327 Cortex-A9 (prior to
1095 r2p0) erratum. The Store Buffer does not have any automatic draining
1096 mechanism and therefore a livelock may occur if an external agent
1097 continuously polls a memory location waiting to observe an update.
1098 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1099 written polling loops from denying visibility of updates to memory.
1101 config ARM_ERRATA_364296
1102 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1105 This options enables the workaround for the 364296 ARM1136
1106 r0p2 erratum (possible cache data corruption with
1107 hit-under-miss enabled). It sets the undocumented bit 31 in
1108 the auxiliary control register and the FI bit in the control
1109 register, thus disabling hit-under-miss without putting the
1110 processor into full low interrupt latency mode. ARM11MPCore
1113 config ARM_ERRATA_764369
1114 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1115 depends on CPU_V7 && SMP
1117 This option enables the workaround for erratum 764369
1118 affecting Cortex-A9 MPCore with two or more processors (all
1119 current revisions). Under certain timing circumstances, a data
1120 cache line maintenance operation by MVA targeting an Inner
1121 Shareable memory region may fail to proceed up to either the
1122 Point of Coherency or to the Point of Unification of the
1123 system. This workaround adds a DSB instruction before the
1124 relevant cache maintenance functions and sets a specific bit
1125 in the diagnostic control register of the SCU.
1127 config ARM_ERRATA_775420
1128 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1131 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1132 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1133 operation aborts with MMU exception, it might cause the processor
1134 to deadlock. This workaround puts DSB before executing ISB if
1135 an abort may occur on cache maintenance.
1137 config ARM_ERRATA_798181
1138 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1139 depends on CPU_V7 && SMP
1141 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1142 adequately shooting down all use of the old entries. This
1143 option enables the Linux kernel workaround for this erratum
1144 which sends an IPI to the CPUs that are running the same ASID
1145 as the one being invalidated.
1147 config ARM_ERRATA_773022
1148 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1151 This option enables the workaround for the 773022 Cortex-A15
1152 (up to r0p4) erratum. In certain rare sequences of code, the
1153 loop buffer may deliver incorrect instructions. This
1154 workaround disables the loop buffer to avoid the erratum.
1156 config ARM_ERRATA_818325_852422
1157 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1160 This option enables the workaround for:
1161 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1162 instruction might deadlock. Fixed in r0p1.
1163 - Cortex-A12 852422: Execution of a sequence of instructions might
1164 lead to either a data corruption or a CPU deadlock. Not fixed in
1165 any Cortex-A12 cores yet.
1166 This workaround for all both errata involves setting bit[12] of the
1167 Feature Register. This bit disables an optimisation applied to a
1168 sequence of 2 instructions that use opposing condition codes.
1170 config ARM_ERRATA_821420
1171 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1174 This option enables the workaround for the 821420 Cortex-A12
1175 (all revs) erratum. In very rare timing conditions, a sequence
1176 of VMOV to Core registers instructions, for which the second
1177 one is in the shadow of a branch or abort, can lead to a
1178 deadlock when the VMOV instructions are issued out-of-order.
1180 config ARM_ERRATA_825619
1181 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1184 This option enables the workaround for the 825619 Cortex-A12
1185 (all revs) erratum. Within rare timing constraints, executing a
1186 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1187 and Device/Strongly-Ordered loads and stores might cause deadlock
1189 config ARM_ERRATA_852421
1190 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1193 This option enables the workaround for the 852421 Cortex-A17
1194 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1195 execution of a DMB ST instruction might fail to properly order
1196 stores from GroupA and stores from GroupB.
1198 config ARM_ERRATA_852423
1199 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1202 This option enables the workaround for:
1203 - Cortex-A17 852423: Execution of a sequence of instructions might
1204 lead to either a data corruption or a CPU deadlock. Not fixed in
1205 any Cortex-A17 cores yet.
1206 This is identical to Cortex-A12 erratum 852422. It is a separate
1207 config option from the A12 erratum due to the way errata are checked
1212 source "arch/arm/common/Kconfig"
1219 Find out whether you have ISA slots on your motherboard. ISA is the
1220 name of a bus system, i.e. the way the CPU talks to the other stuff
1221 inside your box. Other bus systems are PCI, EISA, MicroChannel
1222 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1223 newer boards don't support it. If you have ISA, say Y, otherwise N.
1225 # Select ISA DMA controller support
1230 # Select ISA DMA interface
1235 bool "PCI support" if MIGHT_HAVE_PCI
1237 Find out whether you have a PCI motherboard. PCI is the name of a
1238 bus system, i.e. the way the CPU talks to the other stuff inside
1239 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1240 VESA. If you have PCI, say Y, otherwise N.
1243 bool "Support for multiple PCI domains"
1246 Enable PCI domains kernel management. Say Y if your machine
1247 has a PCI bus hierarchy that requires more than one PCI
1248 domain (aka segment) to be correctly managed. Say N otherwise.
1250 If you don't know what to do here, say N.
1252 config PCI_DOMAINS_GENERIC
1253 def_bool PCI_DOMAINS
1255 config PCI_NANOENGINE
1256 bool "BSE nanoEngine PCI support"
1257 depends on SA1100_NANOENGINE
1259 Enable PCI on the BSE nanoEngine board.
1264 config PCI_HOST_ITE8152
1266 depends on PCI && MACH_ARMCORE
1270 source "drivers/pci/Kconfig"
1272 source "drivers/pcmcia/Kconfig"
1276 menu "Kernel Features"
1281 This option should be selected by machines which have an SMP-
1284 The only effect of this option is to make the SMP-related
1285 options available to the user for configuration.
1288 bool "Symmetric Multi-Processing"
1289 depends on CPU_V6K || CPU_V7
1290 depends on GENERIC_CLOCKEVENTS
1292 depends on MMU || ARM_MPU
1295 This enables support for systems with more than one CPU. If you have
1296 a system with only one CPU, say N. If you have a system with more
1297 than one CPU, say Y.
1299 If you say N here, the kernel will run on uni- and multiprocessor
1300 machines, but will use only one CPU of a multiprocessor machine. If
1301 you say Y here, the kernel will run on many, but not all,
1302 uniprocessor machines. On a uniprocessor machine, the kernel
1303 will run faster if you say N here.
1305 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1306 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at
1307 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1309 If you don't know what to do here, say N.
1312 bool "Allow booting SMP kernel on uniprocessor systems"
1313 depends on SMP && !XIP_KERNEL && MMU
1316 SMP kernels contain instructions which fail on non-SMP processors.
1317 Enabling this option allows the kernel to modify itself to make
1318 these instructions safe. Disabling it allows about 1K of space
1321 If you don't know what to do here, say Y.
1323 config ARM_CPU_TOPOLOGY
1324 bool "Support cpu topology definition"
1325 depends on SMP && CPU_V7
1328 Support ARM cpu topology definition. The MPIDR register defines
1329 affinity between processors which is then used to describe the cpu
1330 topology of an ARM System.
1333 bool "Multi-core scheduler support"
1334 depends on ARM_CPU_TOPOLOGY
1336 Multi-core scheduler support improves the CPU scheduler's decision
1337 making when dealing with multi-core CPU chips at a cost of slightly
1338 increased overhead in some places. If unsure say N here.
1341 bool "SMT scheduler support"
1342 depends on ARM_CPU_TOPOLOGY
1344 Improves the CPU scheduler's decision making when dealing with
1345 MultiThreading at a cost of slightly increased overhead in some
1346 places. If unsure say N here.
1351 This option enables support for the ARM system coherency unit
1353 config HAVE_ARM_ARCH_TIMER
1354 bool "Architected timer support"
1356 select ARM_ARCH_TIMER
1357 select GENERIC_CLOCKEVENTS
1359 This option enables support for the ARM architected timer
1363 select TIMER_OF if OF
1365 This options enables support for the ARM timer and watchdog unit
1368 bool "Multi-Cluster Power Management"
1369 depends on CPU_V7 && SMP
1371 This option provides the common power management infrastructure
1372 for (multi-)cluster based systems, such as big.LITTLE based
1375 config MCPM_QUAD_CLUSTER
1379 To avoid wasting resources unnecessarily, MCPM only supports up
1380 to 2 clusters by default.
1381 Platforms with 3 or 4 clusters that use MCPM must select this
1382 option to allow the additional clusters to be managed.
1385 bool "big.LITTLE support (Experimental)"
1386 depends on CPU_V7 && SMP
1389 This option enables support selections for the big.LITTLE
1390 system architecture.
1393 bool "big.LITTLE switcher support"
1394 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1397 The big.LITTLE "switcher" provides the core functionality to
1398 transparently handle transition between a cluster of A15's
1399 and a cluster of A7's in a big.LITTLE system.
1401 config BL_SWITCHER_DUMMY_IF
1402 tristate "Simple big.LITTLE switcher user interface"
1403 depends on BL_SWITCHER && DEBUG_KERNEL
1405 This is a simple and dummy char dev interface to control
1406 the big.LITTLE switcher core code. It is meant for
1407 debugging purposes only.
1410 prompt "Memory split"
1414 Select the desired split between kernel and user memory.
1416 If you are not absolutely sure what you are doing, leave this
1420 bool "3G/1G user/kernel split"
1421 config VMSPLIT_3G_OPT
1422 depends on !ARM_LPAE
1423 bool "3G/1G user/kernel split (for full 1G low memory)"
1425 bool "2G/2G user/kernel split"
1427 bool "1G/3G user/kernel split"
1432 default PHYS_OFFSET if !MMU
1433 default 0x40000000 if VMSPLIT_1G
1434 default 0x80000000 if VMSPLIT_2G
1435 default 0xB0000000 if VMSPLIT_3G_OPT
1439 int "Maximum number of CPUs (2-32)"
1445 bool "Support for hot-pluggable CPUs"
1448 Say Y here to experiment with turning CPUs off and on. CPUs
1449 can be controlled through /sys/devices/system/cpu.
1452 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1453 depends on HAVE_ARM_SMCCC
1456 Say Y here if you want Linux to communicate with system firmware
1457 implementing the PSCI specification for CPU-centric power
1458 management operations described in ARM document number ARM DEN
1459 0022A ("Power State Coordination Interface System Software on
1462 # The GPIO number here must be sorted by descending number. In case of
1463 # a multiplatform kernel, we just want the highest value required by the
1464 # selected platforms.
1467 default 2048 if ARCH_SOCFPGA
1468 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1470 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1471 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1472 default 416 if ARCH_SUNXI
1473 default 392 if ARCH_U8500
1474 default 352 if ARCH_VT8500
1475 default 288 if ARCH_ROCKCHIP
1476 default 264 if MACH_H4700
1479 Maximum number of GPIOs in the system.
1481 If unsure, leave the default value.
1483 source kernel/Kconfig.preempt
1487 default 200 if ARCH_EBSA110
1488 default 128 if SOC_AT91RM9200
1492 depends on HZ_FIXED = 0
1493 prompt "Timer frequency"
1517 default HZ_FIXED if HZ_FIXED != 0
1518 default 100 if HZ_100
1519 default 200 if HZ_200
1520 default 250 if HZ_250
1521 default 300 if HZ_300
1522 default 500 if HZ_500
1526 def_bool HIGH_RES_TIMERS
1528 config THUMB2_KERNEL
1529 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1530 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1531 default y if CPU_THUMBONLY
1534 By enabling this option, the kernel will be compiled in
1539 config THUMB2_AVOID_R_ARM_THM_JUMP11
1540 bool "Work around buggy Thumb-2 short branch relocations in gas"
1541 depends on THUMB2_KERNEL && MODULES
1544 Various binutils versions can resolve Thumb-2 branches to
1545 locally-defined, preemptible global symbols as short-range "b.n"
1546 branch instructions.
1548 This is a problem, because there's no guarantee the final
1549 destination of the symbol, or any candidate locations for a
1550 trampoline, are within range of the branch. For this reason, the
1551 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1552 relocation in modules at all, and it makes little sense to add
1555 The symptom is that the kernel fails with an "unsupported
1556 relocation" error when loading some modules.
1558 Until fixed tools are available, passing
1559 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1560 code which hits this problem, at the cost of a bit of extra runtime
1561 stack usage in some cases.
1563 The problem is described in more detail at:
1564 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1566 Only Thumb-2 kernels are affected.
1568 Unless you are sure your tools don't have this problem, say Y.
1570 config ARM_PATCH_IDIV
1571 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1572 depends on CPU_32v7 && !XIP_KERNEL
1575 The ARM compiler inserts calls to __aeabi_idiv() and
1576 __aeabi_uidiv() when it needs to perform division on signed
1577 and unsigned integers. Some v7 CPUs have support for the sdiv
1578 and udiv instructions that can be used to implement those
1581 Enabling this option allows the kernel to modify itself to
1582 replace the first two instructions of these library functions
1583 with the sdiv or udiv plus "bx lr" instructions when the CPU
1584 it is running on supports them. Typically this will be faster
1585 and less power intensive than running the original library
1586 code to do integer division.
1589 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1590 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1592 This option allows for the kernel to be compiled using the latest
1593 ARM ABI (aka EABI). This is only useful if you are using a user
1594 space environment that is also compiled with EABI.
1596 Since there are major incompatibilities between the legacy ABI and
1597 EABI, especially with regard to structure member alignment, this
1598 option also changes the kernel syscall calling convention to
1599 disambiguate both ABIs and allow for backward compatibility support
1600 (selected with CONFIG_OABI_COMPAT).
1602 To use this you need GCC version 4.0.0 or later.
1605 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1606 depends on AEABI && !THUMB2_KERNEL
1608 This option preserves the old syscall interface along with the
1609 new (ARM EABI) one. It also provides a compatibility layer to
1610 intercept syscalls that have structure arguments which layout
1611 in memory differs between the legacy ABI and the new ARM EABI
1612 (only for non "thumb" binaries). This option adds a tiny
1613 overhead to all syscalls and produces a slightly larger kernel.
1615 The seccomp filter system will not be available when this is
1616 selected, since there is no way yet to sensibly distinguish
1617 between calling conventions during filtering.
1619 If you know you'll be using only pure EABI user space then you
1620 can say N here. If this option is not selected and you attempt
1621 to execute a legacy ABI binary then the result will be
1622 UNPREDICTABLE (in fact it can be predicted that it won't work
1623 at all). If in doubt say N.
1625 config ARCH_HAS_HOLES_MEMORYMODEL
1628 config ARCH_SPARSEMEM_ENABLE
1631 config ARCH_SPARSEMEM_DEFAULT
1632 def_bool ARCH_SPARSEMEM_ENABLE
1634 config ARCH_SELECT_MEMORY_MODEL
1635 def_bool ARCH_SPARSEMEM_ENABLE
1637 config HAVE_ARCH_PFN_VALID
1638 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1640 config HAVE_GENERIC_GUP
1645 bool "High Memory Support"
1648 The address space of ARM processors is only 4 Gigabytes large
1649 and it has to accommodate user address space, kernel address
1650 space as well as some memory mapped IO. That means that, if you
1651 have a large amount of physical memory and/or IO, not all of the
1652 memory can be "permanently mapped" by the kernel. The physical
1653 memory that is not permanently mapped is called "high memory".
1655 Depending on the selected kernel/user memory split, minimum
1656 vmalloc space and actual amount of RAM, you may not need this
1657 option which should result in a slightly faster kernel.
1662 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1666 The VM uses one page of physical memory for each page table.
1667 For systems with a lot of processes, this can use a lot of
1668 precious low memory, eventually leading to low memory being
1669 consumed by page tables. Setting this option will allow
1670 user-space 2nd level page tables to reside in high memory.
1672 config CPU_SW_DOMAIN_PAN
1673 bool "Enable use of CPU domains to implement privileged no-access"
1674 depends on MMU && !ARM_LPAE
1677 Increase kernel security by ensuring that normal kernel accesses
1678 are unable to access userspace addresses. This can help prevent
1679 use-after-free bugs becoming an exploitable privilege escalation
1680 by ensuring that magic values (such as LIST_POISON) will always
1681 fault when dereferenced.
1683 CPUs with low-vector mappings use a best-efforts implementation.
1684 Their lower 1MB needs to remain accessible for the vectors, but
1685 the remainder of userspace will become appropriately inaccessible.
1687 config HW_PERF_EVENTS
1691 config SYS_SUPPORTS_HUGETLBFS
1695 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1699 config ARCH_WANT_GENERAL_HUGETLB
1702 config ARM_MODULE_PLTS
1703 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1707 Allocate PLTs when loading modules so that jumps and calls whose
1708 targets are too far away for their relative offsets to be encoded
1709 in the instructions themselves can be bounced via veneers in the
1710 module's PLT. This allows modules to be allocated in the generic
1711 vmalloc area after the dedicated module memory area has been
1712 exhausted. The modules will use slightly more memory, but after
1713 rounding up to page size, the actual memory footprint is usually
1716 Disabling this is usually safe for small single-platform
1717 configurations. If unsure, say y.
1721 config FORCE_MAX_ZONEORDER
1722 int "Maximum zone order"
1723 default "12" if SOC_AM33XX
1724 default "9" if SA1111 || ARCH_EFM32
1727 The kernel memory allocator divides physically contiguous memory
1728 blocks into "zones", where each zone is a power of two number of
1729 pages. This option selects the largest power of two that the kernel
1730 keeps in the memory allocator. If you need to allocate very large
1731 blocks of physically contiguous memory, then you may need to
1732 increase this value.
1734 This config option is actually maximum order plus one. For example,
1735 a value of 11 means that the largest free memory block is 2^10 pages.
1737 config ALIGNMENT_TRAP
1739 depends on CPU_CP15_MMU
1740 default y if !ARCH_EBSA110
1741 select HAVE_PROC_CPU if PROC_FS
1743 ARM processors cannot fetch/store information which is not
1744 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1745 address divisible by 4. On 32-bit ARM processors, these non-aligned
1746 fetch/store instructions will be emulated in software if you say
1747 here, which has a severe performance impact. This is necessary for
1748 correct operation of some network protocols. With an IP-only
1749 configuration it is safe to say N, otherwise say Y.
1751 config UACCESS_WITH_MEMCPY
1752 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1754 default y if CPU_FEROCEON
1756 Implement faster copy_to_user and clear_user methods for CPU
1757 cores where a 8-word STM instruction give significantly higher
1758 memory write throughput than a sequence of individual 32bit stores.
1760 A possible side effect is a slight increase in scheduling latency
1761 between threads sharing the same address space if they invoke
1762 such copy operations with large buffers.
1764 However, if the CPU data cache is using a write-allocate mode,
1765 this option is unlikely to provide any performance gain.
1769 prompt "Enable seccomp to safely compute untrusted bytecode"
1771 This kernel feature is useful for number crunching applications
1772 that may need to compute untrusted bytecode during their
1773 execution. By using pipes or other transports made available to
1774 the process as file descriptors supporting the read/write
1775 syscalls, it's possible to isolate those applications in
1776 their own address space using seccomp. Once seccomp is
1777 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1778 and the task is only allowed to execute a few safe syscalls
1779 defined by each seccomp mode.
1782 bool "Enable paravirtualization code"
1784 This changes the kernel so it can modify itself when it is run
1785 under a hypervisor, potentially improving performance significantly
1786 over full virtualization.
1788 config PARAVIRT_TIME_ACCOUNTING
1789 bool "Paravirtual steal time accounting"
1793 Select this option to enable fine granularity task steal time
1794 accounting. Time spent executing other tasks in parallel with
1795 the current vCPU is discounted from the vCPU power. To account for
1796 that, there can be a small performance impact.
1798 If in doubt, say N here.
1805 bool "Xen guest support on ARM"
1806 depends on ARM && AEABI && OF
1807 depends on CPU_V7 && !CPU_V6
1808 depends on !GENERIC_ATOMIC64
1810 select ARCH_DMA_ADDR_T_64BIT
1816 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1823 bool "Flattened Device Tree support"
1827 Include support for flattened device tree machine descriptions.
1830 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1833 This is the traditional way of passing data to the kernel at boot
1834 time. If you are solely relying on the flattened device tree (or
1835 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1836 to remove ATAGS support from your kernel binary. If unsure,
1839 config DEPRECATED_PARAM_STRUCT
1840 bool "Provide old way to pass kernel parameters"
1843 This was deprecated in 2001 and announced to live on for 5 years.
1844 Some old boot loaders still use this way.
1846 # Compressed boot loader in ROM. Yes, we really want to ask about
1847 # TEXT and BSS so we preserve their values in the config files.
1848 config ZBOOT_ROM_TEXT
1849 hex "Compressed ROM boot loader base address"
1852 The physical address at which the ROM-able zImage is to be
1853 placed in the target. Platforms which normally make use of
1854 ROM-able zImage formats normally set this to a suitable
1855 value in their defconfig file.
1857 If ZBOOT_ROM is not enabled, this has no effect.
1859 config ZBOOT_ROM_BSS
1860 hex "Compressed ROM boot loader BSS address"
1863 The base address of an area of read/write memory in the target
1864 for the ROM-able zImage which must be available while the
1865 decompressor is running. It must be large enough to hold the
1866 entire decompressed kernel plus an additional 128 KiB.
1867 Platforms which normally make use of ROM-able zImage formats
1868 normally set this to a suitable value in their defconfig file.
1870 If ZBOOT_ROM is not enabled, this has no effect.
1873 bool "Compressed boot loader in ROM/flash"
1874 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1875 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1877 Say Y here if you intend to execute your compressed kernel image
1878 (zImage) directly from ROM or flash. If unsure, say N.
1880 config ARM_APPENDED_DTB
1881 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1884 With this option, the boot code will look for a device tree binary
1885 (DTB) appended to zImage
1886 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1888 This is meant as a backward compatibility convenience for those
1889 systems with a bootloader that can't be upgraded to accommodate
1890 the documented boot protocol using a device tree.
1892 Beware that there is very little in terms of protection against
1893 this option being confused by leftover garbage in memory that might
1894 look like a DTB header after a reboot if no actual DTB is appended
1895 to zImage. Do not leave this option active in a production kernel
1896 if you don't intend to always append a DTB. Proper passing of the
1897 location into r2 of a bootloader provided DTB is always preferable
1900 config ARM_ATAG_DTB_COMPAT
1901 bool "Supplement the appended DTB with traditional ATAG information"
1902 depends on ARM_APPENDED_DTB
1904 Some old bootloaders can't be updated to a DTB capable one, yet
1905 they provide ATAGs with memory configuration, the ramdisk address,
1906 the kernel cmdline string, etc. Such information is dynamically
1907 provided by the bootloader and can't always be stored in a static
1908 DTB. To allow a device tree enabled kernel to be used with such
1909 bootloaders, this option allows zImage to extract the information
1910 from the ATAG list and store it at run time into the appended DTB.
1913 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1914 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1916 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1917 bool "Use bootloader kernel arguments if available"
1919 Uses the command-line options passed by the boot loader instead of
1920 the device tree bootargs property. If the boot loader doesn't provide
1921 any, the device tree bootargs property will be used.
1923 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1924 bool "Extend with bootloader kernel arguments"
1926 The command-line arguments provided by the boot loader will be
1927 appended to the the device tree bootargs property.
1932 string "Default kernel command string"
1935 On some architectures (EBSA110 and CATS), there is currently no way
1936 for the boot loader to pass arguments to the kernel. For these
1937 architectures, you should supply some command-line options at build
1938 time by entering them here. As a minimum, you should specify the
1939 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1942 prompt "Kernel command line type" if CMDLINE != ""
1943 default CMDLINE_FROM_BOOTLOADER
1946 config CMDLINE_FROM_BOOTLOADER
1947 bool "Use bootloader kernel arguments if available"
1949 Uses the command-line options passed by the boot loader. If
1950 the boot loader doesn't provide any, the default kernel command
1951 string provided in CMDLINE will be used.
1953 config CMDLINE_EXTEND
1954 bool "Extend bootloader kernel arguments"
1956 The command-line arguments provided by the boot loader will be
1957 appended to the default kernel command string.
1959 config CMDLINE_FORCE
1960 bool "Always use the default kernel command string"
1962 Always use the default kernel command string, even if the boot
1963 loader passes other arguments to the kernel.
1964 This is useful if you cannot or don't want to change the
1965 command-line options your boot loader passes to the kernel.
1969 bool "Kernel Execute-In-Place from ROM"
1970 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1972 Execute-In-Place allows the kernel to run from non-volatile storage
1973 directly addressable by the CPU, such as NOR flash. This saves RAM
1974 space since the text section of the kernel is not loaded from flash
1975 to RAM. Read-write sections, such as the data section and stack,
1976 are still copied to RAM. The XIP kernel is not compressed since
1977 it has to run directly from flash, so it will take more space to
1978 store it. The flash address used to link the kernel object files,
1979 and for storing it, is configuration dependent. Therefore, if you
1980 say Y here, you must know the proper physical address where to
1981 store the kernel image depending on your own flash memory usage.
1983 Also note that the make target becomes "make xipImage" rather than
1984 "make zImage" or "make Image". The final kernel binary to put in
1985 ROM memory will be arch/arm/boot/xipImage.
1989 config XIP_PHYS_ADDR
1990 hex "XIP Kernel Physical Location"
1991 depends on XIP_KERNEL
1992 default "0x00080000"
1994 This is the physical address in your flash memory the kernel will
1995 be linked for and stored to. This address is dependent on your
1998 config XIP_DEFLATED_DATA
1999 bool "Store kernel .data section compressed in ROM"
2000 depends on XIP_KERNEL
2003 Before the kernel is actually executed, its .data section has to be
2004 copied to RAM from ROM. This option allows for storing that data
2005 in compressed form and decompressed to RAM rather than merely being
2006 copied, saving some precious ROM space. A possible drawback is a
2007 slightly longer boot delay.
2010 bool "Kexec system call (EXPERIMENTAL)"
2011 depends on (!SMP || PM_SLEEP_SMP)
2015 kexec is a system call that implements the ability to shutdown your
2016 current kernel, and to start another kernel. It is like a reboot
2017 but it is independent of the system firmware. And like a reboot
2018 you can start any kernel with it, not just Linux.
2020 It is an ongoing process to be certain the hardware in a machine
2021 is properly shutdown, so do not be surprised if this code does not
2022 initially work for you.
2025 bool "Export atags in procfs"
2026 depends on ATAGS && KEXEC
2029 Should the atags used to boot the kernel be exported in an "atags"
2030 file in procfs. Useful with kexec.
2033 bool "Build kdump crash kernel (EXPERIMENTAL)"
2035 Generate crash dump after being started by kexec. This should
2036 be normally only set in special crash dump kernels which are
2037 loaded in the main kernel with kexec-tools into a specially
2038 reserved region and then later executed after a crash by
2039 kdump/kexec. The crash dump kernel must be compiled to a
2040 memory address not used by the main kernel
2042 For more details see Documentation/kdump/kdump.txt
2044 config AUTO_ZRELADDR
2045 bool "Auto calculation of the decompressed kernel image address"
2047 ZRELADDR is the physical address where the decompressed kernel
2048 image will be placed. If AUTO_ZRELADDR is selected, the address
2049 will be determined at run-time by masking the current IP with
2050 0xf8000000. This assumes the zImage being placed in the first 128MB
2051 from start of memory.
2057 bool "UEFI runtime support"
2058 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2060 select EFI_PARAMS_FROM_FDT
2063 select EFI_RUNTIME_WRAPPERS
2065 This option provides support for runtime services provided
2066 by UEFI firmware (such as non-volatile variables, realtime
2067 clock, and platform reset). A UEFI stub is also provided to
2068 allow the kernel to be booted as an EFI application. This
2069 is only useful for kernels that may run on systems that have
2073 bool "Enable support for SMBIOS (DMI) tables"
2077 This enables SMBIOS/DMI feature for systems.
2079 This option is only useful on systems that have UEFI firmware.
2080 However, even with this option, the resultant kernel should
2081 continue to boot on existing non-UEFI platforms.
2083 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2084 i.e., the the practice of identifying the platform via DMI to
2085 decide whether certain workarounds for buggy hardware and/or
2086 firmware need to be enabled. This would require the DMI subsystem
2087 to be enabled much earlier than we do on ARM, which is non-trivial.
2091 menu "CPU Power Management"
2093 source "drivers/cpufreq/Kconfig"
2095 source "drivers/cpuidle/Kconfig"
2099 menu "Floating point emulation"
2101 comment "At least one emulation must be selected"
2104 bool "NWFPE math emulation"
2105 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2107 Say Y to include the NWFPE floating point emulator in the kernel.
2108 This is necessary to run most binaries. Linux does not currently
2109 support floating point hardware so you need to say Y here even if
2110 your machine has an FPA or floating point co-processor podule.
2112 You may say N here if you are going to load the Acorn FPEmulator
2113 early in the bootup.
2116 bool "Support extended precision"
2117 depends on FPE_NWFPE
2119 Say Y to include 80-bit support in the kernel floating-point
2120 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2121 Note that gcc does not generate 80-bit operations by default,
2122 so in most cases this option only enlarges the size of the
2123 floating point emulator without any good reason.
2125 You almost surely want to say N here.
2128 bool "FastFPE math emulation (EXPERIMENTAL)"
2129 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2131 Say Y here to include the FAST floating point emulator in the kernel.
2132 This is an experimental much faster emulator which now also has full
2133 precision for the mantissa. It does not support any exceptions.
2134 It is very simple, and approximately 3-6 times faster than NWFPE.
2136 It should be sufficient for most programs. It may be not suitable
2137 for scientific calculations, but you have to check this for yourself.
2138 If you do not feel you need a faster FP emulation you should better
2142 bool "VFP-format floating point maths"
2143 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2145 Say Y to include VFP support code in the kernel. This is needed
2146 if your hardware includes a VFP unit.
2148 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2149 release notes and additional status information.
2151 Say N if your target does not have VFP hardware.
2159 bool "Advanced SIMD (NEON) Extension support"
2160 depends on VFPv3 && CPU_V7
2162 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2165 config KERNEL_MODE_NEON
2166 bool "Support for NEON in kernel mode"
2167 depends on NEON && AEABI
2169 Say Y to include support for NEON in kernel mode.
2173 menu "Userspace binary formats"
2175 source "fs/Kconfig.binfmt"
2179 menu "Power management options"
2181 source "kernel/power/Kconfig"
2183 config ARCH_SUSPEND_POSSIBLE
2184 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2185 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2188 config ARM_CPU_SUSPEND
2189 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2190 depends on ARCH_SUSPEND_POSSIBLE
2192 config ARCH_HIBERNATION_POSSIBLE
2195 default y if ARCH_SUSPEND_POSSIBLE
2199 source "net/Kconfig"
2201 source "drivers/Kconfig"
2203 source "drivers/firmware/Kconfig"
2207 source "arch/arm/Kconfig.debug"
2209 source "security/Kconfig"
2211 source "crypto/Kconfig"
2213 source "arch/arm/crypto/Kconfig"
2216 source "lib/Kconfig"
2218 source "arch/arm/kvm/Kconfig"