1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND
7 select ARCH_HAS_BINFMT_FLAT
8 select ARCH_HAS_CURRENT_STACK_POINTER
9 select ARCH_HAS_DEBUG_VIRTUAL if MMU
10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
11 select ARCH_HAS_ELF_RANDOMIZE
12 select ARCH_HAS_FORTIFY_SOURCE
13 select ARCH_HAS_KEEPINITRD
15 select ARCH_HAS_MEMBARRIER_SYNC_CORE
16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
18 select ARCH_HAS_PHYS_TO_DMA
19 select ARCH_HAS_SETUP_DMA_OPS
20 select ARCH_HAS_SET_MEMORY
21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
22 select ARCH_HAS_STRICT_MODULE_RWX if MMU
23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU
24 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU
25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
27 select ARCH_HAVE_CUSTOM_GPIO_H
28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
29 select ARCH_HAS_GCOV_PROFILE_ALL
30 select ARCH_KEEP_MEMBLOCK
31 select ARCH_MIGHT_HAVE_PC_PARPORT
32 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
35 select ARCH_SUPPORTS_ATOMIC_RMW
36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
37 select ARCH_USE_BUILTIN_BSWAP
38 select ARCH_USE_CMPXCHG_LOCKREF
39 select ARCH_USE_MEMTEST
40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
41 select ARCH_WANT_GENERAL_HUGETLB
42 select ARCH_WANT_IPC_PARSE_VERSION
43 select ARCH_WANT_LD_ORPHAN_WARN
44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
45 select BUILDTIME_TABLE_SORT if MMU
46 select CLONE_BACKWARDS
47 select CPU_PM if SUSPEND || CPU_IDLE
48 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
49 select DMA_DECLARE_COHERENT
50 select DMA_GLOBAL_POOL if !MMU
52 select DMA_REMAP if MMU
54 select EDAC_ATOMIC_SCRUB
55 select GENERIC_ALLOCATOR
56 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
57 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
58 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
59 select GENERIC_IRQ_IPI if SMP
60 select GENERIC_CPU_AUTOPROBE
61 select GENERIC_EARLY_IOREMAP
62 select GENERIC_IDLE_POLL_SETUP
63 select GENERIC_IRQ_MULTI_HANDLER
64 select GENERIC_IRQ_PROBE
65 select GENERIC_IRQ_SHOW
66 select GENERIC_IRQ_SHOW_LEVEL
67 select GENERIC_LIB_DEVMEM_IS_ALLOWED
68 select GENERIC_PCI_IOMAP
69 select GENERIC_SCHED_CLOCK
70 select GENERIC_SMP_IDLE_THREAD
71 select HARDIRQS_SW_RESEND
72 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
73 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
74 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
75 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL
76 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
77 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
78 select HAVE_ARCH_MMAP_RND_BITS if MMU
79 select HAVE_ARCH_PFN_VALID
80 select HAVE_ARCH_SECCOMP
81 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
82 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
83 select HAVE_ARCH_TRACEHOOK
84 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
85 select HAVE_ARM_SMCCC if CPU_V7
86 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
87 select HAVE_CONTEXT_TRACKING
88 select HAVE_C_RECORDMCOUNT
89 select HAVE_BUILDTIME_MCOUNT_SORT
90 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
91 select HAVE_DMA_CONTIGUOUS if MMU
92 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
93 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
94 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
95 select HAVE_EXIT_THREAD
96 select HAVE_FAST_GUP if ARM_LPAE
97 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
98 select HAVE_FUNCTION_GRAPH_TRACER
99 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
100 select HAVE_GCC_PLUGINS
101 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
102 select HAVE_IRQ_TIME_ACCOUNTING
103 select HAVE_KERNEL_GZIP
104 select HAVE_KERNEL_LZ4
105 select HAVE_KERNEL_LZMA
106 select HAVE_KERNEL_LZO
107 select HAVE_KERNEL_XZ
108 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
109 select HAVE_KRETPROBES if HAVE_KPROBES
110 select HAVE_MOD_ARCH_SPECIFIC
112 select HAVE_OPTPROBES if !THUMB2_KERNEL
113 select HAVE_PERF_EVENTS
114 select HAVE_PERF_REGS
115 select HAVE_PERF_USER_STACK_DUMP
116 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
117 select HAVE_REGS_AND_STACK_ACCESS_API
119 select HAVE_STACKPROTECTOR
120 select HAVE_SYSCALL_TRACEPOINTS
122 select HAVE_VIRT_CPU_ACCOUNTING_GEN
123 select IRQ_FORCED_THREADING
124 select MODULES_USE_ELF_REL
125 select NEED_DMA_MAP_STATE
126 select OF_EARLY_FLATTREE if OF
128 select OLD_SIGSUSPEND3
129 select PCI_SYSCALL if PCI
130 select PERF_USE_VMALLOC
132 select SYS_SUPPORTS_APM_EMULATION
133 select THREAD_INFO_IN_TASK
134 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS
135 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
136 # Above selects are sorted alphabetically; please add new ones
137 # according to that. Thanks.
139 The ARM series is a line of low-power-consumption RISC chip designs
140 licensed by ARM Ltd and targeted at embedded applications and
141 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
142 manufactured, but legacy ARM-based PC hardware remains popular in
143 Europe. There is an ARM Linux project with a web page at
144 <http://www.arm.linux.org.uk/>.
146 config ARM_HAS_GROUP_RELOCS
148 depends on !LD_IS_LLD || LLD_VERSION >= 140000
149 depends on !COMPILE_TEST
151 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group
152 relocations, which have been around for a long time, but were not
153 supported in LLD until version 14. The combined range is -/+ 256 MiB,
154 which is usually sufficient, but not for allyesconfig, so we disable
155 this feature when doing compile testing.
157 config ARM_HAS_SG_CHAIN
160 config ARM_DMA_USE_IOMMU
162 select ARM_HAS_SG_CHAIN
163 select NEED_SG_DMA_LENGTH
167 config ARM_DMA_IOMMU_ALIGNMENT
168 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
172 DMA mapping framework by default aligns all buffers to the smallest
173 PAGE_SIZE order which is greater than or equal to the requested buffer
174 size. This works well for buffers up to a few hundreds kilobytes, but
175 for larger buffers it just a waste of address space. Drivers which has
176 relatively small addressing window (like 64Mib) might run out of
177 virtual space with just a few allocations.
179 With this parameter you can specify the maximum PAGE_SIZE order for
180 DMA IOMMU buffers. Larger buffers will be aligned only to this
181 specified order. The order is expressed as a power of two multiplied
186 config SYS_SUPPORTS_APM_EMULATION
191 select GENERIC_ALLOCATOR
202 config STACKTRACE_SUPPORT
206 config LOCKDEP_SUPPORT
210 config ARCH_HAS_ILOG2_U32
213 config ARCH_HAS_ILOG2_U64
216 config ARCH_HAS_BANDGAP
219 config FIX_EARLYCON_MEM
222 config GENERIC_HWEIGHT
226 config GENERIC_CALIBRATE_DELAY
230 config ARCH_MAY_HAVE_PC_FDC
233 config ARCH_SUPPORTS_UPROBES
236 config ARCH_HAS_DMA_SET_COHERENT_MASK
239 config GENERIC_ISA_DMA
248 config ARM_PATCH_PHYS_VIRT
249 bool "Patch physical to virtual translations at runtime" if EMBEDDED
251 depends on !XIP_KERNEL && MMU
253 Patch phys-to-virt and virt-to-phys translation functions at
254 boot and module load time according to the position of the
255 kernel in system memory.
257 This can only be used with non-XIP MMU kernels where the base
258 of physical memory is at a 2 MiB boundary.
260 Only disable this option if you know that you do not require
261 this feature (eg, building a kernel for a single machine) and
262 you need to shrink the kernel to the minimal size.
264 config NEED_MACH_IO_H
267 Select this when mach/io.h is required to provide special
268 definitions for this platform. The need for mach/io.h should
269 be avoided when possible.
271 config NEED_MACH_MEMORY_H
274 Select this when mach/memory.h is required to provide special
275 definitions for this platform. The need for mach/memory.h should
276 be avoided when possible.
279 hex "Physical address of main memory" if MMU
280 depends on !ARM_PATCH_PHYS_VIRT
281 default DRAM_BASE if !MMU
282 default 0x00000000 if ARCH_FOOTBRIDGE || ARCH_IXP4XX
283 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
284 default 0x30000000 if ARCH_S3C24XX
285 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA
286 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
289 Please provide the physical address corresponding to the
290 location of main memory in your system.
296 config PGTABLE_LEVELS
298 default 3 if ARM_LPAE
304 bool "MMU-based Paged Memory Management Support"
307 Select if you want MMU-based virtualised addressing space
308 support by paged memory management. If unsure, say 'Y'.
310 config ARCH_MMAP_RND_BITS_MIN
313 config ARCH_MMAP_RND_BITS_MAX
314 default 14 if PAGE_OFFSET=0x40000000
315 default 15 if PAGE_OFFSET=0x80000000
319 # The "ARM system type" choice list is ordered alphabetically by option
320 # text. Please add new entries in the option alphabetic order.
323 prompt "ARM system type"
324 default ARM_SINGLE_ARMV7M if !MMU
325 default ARCH_MULTIPLATFORM if MMU
327 config ARCH_MULTIPLATFORM
328 bool "Allow multiple platforms to be selected"
330 select ARCH_FLATMEM_ENABLE
331 select ARCH_SPARSEMEM_ENABLE
332 select ARCH_SELECT_MEMORY_MODEL
333 select ARM_HAS_SG_CHAIN
334 select ARM_PATCH_PHYS_VIRT
339 select PCI_DOMAINS_GENERIC if PCI
343 config ARM_SINGLE_ARMV7M
344 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
357 select ARCH_SPARSEMEM_ENABLE
359 imply ARM_PATCH_PHYS_VIRT
367 This enables support for the Cirrus EP93xx series of CPUs.
369 config ARCH_FOOTBRIDGE
373 select NEED_MACH_IO_H if !MMU
374 select NEED_MACH_MEMORY_H
376 Support for systems based on the DC21285 companion chip
377 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
388 Support for Intel's 80219 and IOP32X (XScale) family of
394 select ARCH_HAS_DMA_SET_COHERENT_MASK
395 select ARCH_SUPPORTS_BIG_ENDIAN
397 select DMABOUNCE if PCI
403 # With the new PCI driver this is not needed
404 select NEED_MACH_IO_H if IXP4XX_PCI_LEGACY
405 select USB_EHCI_BIG_ENDIAN_DESC
406 select USB_EHCI_BIG_ENDIAN_MMIO
408 Support for Intel's IXP4XX (XScale) family of processors.
418 select PLAT_ORION_LEGACY
420 select PM_GENERIC_DOMAINS if PM
422 Support for the Marvell Dove SoC 88AP510
425 bool "PXA2xx/PXA3xx-based"
428 select ARM_CPU_SUSPEND if PM
434 select CPU_XSCALE if !CPU_XSC3
441 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
446 depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000
448 select ARCH_MAY_HAVE_PC_FDC
449 select ARCH_SPARSEMEM_ENABLE
450 select ARM_HAS_SG_CHAIN
453 select HAVE_PATA_PLATFORM
455 select LEGACY_TIMER_TICK
456 select NEED_MACH_IO_H
457 select NEED_MACH_MEMORY_H
460 On the Acorn Risc-PC, Linux can support the internal IDE disk and
461 CD-ROM interface, serial and parallel port, and the floppy drive.
466 select ARCH_SPARSEMEM_ENABLE
469 select TIMER_OF if OF
476 select NEED_MACH_MEMORY_H
479 Support for StrongARM 11x0 based boards.
482 bool "Samsung S3C24XX SoCs"
484 select CLKSRC_SAMSUNG_PWM
487 select NEED_MACH_IO_H
488 select S3C2410_WATCHDOG
493 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
494 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
495 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
496 Samsung SMDK2410 development board (and derivatives).
503 select GENERIC_IRQ_CHIP
505 select HAVE_LEGACY_CLK
507 select NEED_MACH_IO_H if PCCARD
508 select NEED_MACH_MEMORY_H
511 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
515 menu "Multiple platform selection"
516 depends on ARCH_MULTIPLATFORM
518 comment "CPU Core family selection"
521 bool "ARMv4 based platforms (FA526)"
522 depends on !ARCH_MULTI_V6_V7
523 select ARCH_MULTI_V4_V5
526 config ARCH_MULTI_V4T
527 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
528 depends on !ARCH_MULTI_V6_V7
529 select ARCH_MULTI_V4_V5
530 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
531 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
532 CPU_ARM925T || CPU_ARM940T)
535 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
536 depends on !ARCH_MULTI_V6_V7
537 select ARCH_MULTI_V4_V5
538 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
539 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
540 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
542 config ARCH_MULTI_V4_V5
546 bool "ARMv6 based platforms (ARM11)"
547 select ARCH_MULTI_V6_V7
551 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
553 select ARCH_MULTI_V6_V7
557 config ARCH_MULTI_V6_V7
559 select MIGHT_HAVE_CACHE_L2X0
561 config ARCH_MULTI_CPU_AUTO
562 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
568 bool "Dummy Virtual Machine"
569 depends on ARCH_MULTI_V7
572 select ARM_GIC_V2M if PCI
574 select ARM_GIC_V3_ITS if PCI
576 select HAVE_ARM_ARCH_TIMER
577 select ARCH_SUPPORTS_BIG_ENDIAN
580 # This is sorted alphabetically by mach-* pathname. However, plat-*
581 # Kconfigs may be included either alphabetically (according to the
582 # plat- suffix) or along side the corresponding mach-* source.
584 source "arch/arm/mach-actions/Kconfig"
586 source "arch/arm/mach-alpine/Kconfig"
588 source "arch/arm/mach-artpec/Kconfig"
590 source "arch/arm/mach-asm9260/Kconfig"
592 source "arch/arm/mach-aspeed/Kconfig"
594 source "arch/arm/mach-at91/Kconfig"
596 source "arch/arm/mach-axxia/Kconfig"
598 source "arch/arm/mach-bcm/Kconfig"
600 source "arch/arm/mach-berlin/Kconfig"
602 source "arch/arm/mach-clps711x/Kconfig"
604 source "arch/arm/mach-cns3xxx/Kconfig"
606 source "arch/arm/mach-davinci/Kconfig"
608 source "arch/arm/mach-digicolor/Kconfig"
610 source "arch/arm/mach-dove/Kconfig"
612 source "arch/arm/mach-ep93xx/Kconfig"
614 source "arch/arm/mach-exynos/Kconfig"
616 source "arch/arm/mach-footbridge/Kconfig"
618 source "arch/arm/mach-gemini/Kconfig"
620 source "arch/arm/mach-highbank/Kconfig"
622 source "arch/arm/mach-hisi/Kconfig"
624 source "arch/arm/mach-imx/Kconfig"
626 source "arch/arm/mach-integrator/Kconfig"
628 source "arch/arm/mach-iop32x/Kconfig"
630 source "arch/arm/mach-ixp4xx/Kconfig"
632 source "arch/arm/mach-keystone/Kconfig"
634 source "arch/arm/mach-lpc32xx/Kconfig"
636 source "arch/arm/mach-mediatek/Kconfig"
638 source "arch/arm/mach-meson/Kconfig"
640 source "arch/arm/mach-milbeaut/Kconfig"
642 source "arch/arm/mach-mmp/Kconfig"
644 source "arch/arm/mach-moxart/Kconfig"
646 source "arch/arm/mach-mstar/Kconfig"
648 source "arch/arm/mach-mv78xx0/Kconfig"
650 source "arch/arm/mach-mvebu/Kconfig"
652 source "arch/arm/mach-mxs/Kconfig"
654 source "arch/arm/mach-nomadik/Kconfig"
656 source "arch/arm/mach-npcm/Kconfig"
658 source "arch/arm/mach-nspire/Kconfig"
660 source "arch/arm/plat-omap/Kconfig"
662 source "arch/arm/mach-omap1/Kconfig"
664 source "arch/arm/mach-omap2/Kconfig"
666 source "arch/arm/mach-orion5x/Kconfig"
668 source "arch/arm/mach-oxnas/Kconfig"
670 source "arch/arm/mach-pxa/Kconfig"
671 source "arch/arm/plat-pxa/Kconfig"
673 source "arch/arm/mach-qcom/Kconfig"
675 source "arch/arm/mach-rda/Kconfig"
677 source "arch/arm/mach-realtek/Kconfig"
679 source "arch/arm/mach-realview/Kconfig"
681 source "arch/arm/mach-rockchip/Kconfig"
683 source "arch/arm/mach-s3c/Kconfig"
685 source "arch/arm/mach-s5pv210/Kconfig"
687 source "arch/arm/mach-sa1100/Kconfig"
689 source "arch/arm/mach-shmobile/Kconfig"
691 source "arch/arm/mach-socfpga/Kconfig"
693 source "arch/arm/mach-spear/Kconfig"
695 source "arch/arm/mach-sti/Kconfig"
697 source "arch/arm/mach-stm32/Kconfig"
699 source "arch/arm/mach-sunxi/Kconfig"
701 source "arch/arm/mach-tegra/Kconfig"
703 source "arch/arm/mach-uniphier/Kconfig"
705 source "arch/arm/mach-ux500/Kconfig"
707 source "arch/arm/mach-versatile/Kconfig"
709 source "arch/arm/mach-vexpress/Kconfig"
711 source "arch/arm/mach-vt8500/Kconfig"
713 source "arch/arm/mach-zynq/Kconfig"
715 # ARMv7-M architecture
717 bool "NXP LPC18xx/LPC43xx"
718 depends on ARM_SINGLE_ARMV7M
719 select ARCH_HAS_RESET_CONTROLLER
721 select CLKSRC_LPC32XX
724 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
725 high performance microcontrollers.
728 bool "ARM MPS2 platform"
729 depends on ARM_SINGLE_ARMV7M
733 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
734 with a range of available cores like Cortex-M3/M4/M7.
736 Please, note that depends which Application Note is used memory map
737 for the platform may vary, so adjustment of RAM base might be needed.
739 # Definitions to make life easier
750 select GENERIC_IRQ_CHIP
753 config PLAT_ORION_LEGACY
760 config PLAT_VERSATILE
763 source "arch/arm/mm/Kconfig"
766 bool "Enable iWMMXt support"
767 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
768 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
770 Enable support for iWMMXt context switching at run time if
771 running on a CPU that supports it.
774 source "arch/arm/Kconfig-nommu"
777 config PJ4B_ERRATA_4742
778 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
779 depends on CPU_PJ4B && MACH_ARMADA_370
782 When coming out of either a Wait for Interrupt (WFI) or a Wait for
783 Event (WFE) IDLE states, a specific timing sensitivity exists between
784 the retiring WFI/WFE instructions and the newly issued subsequent
785 instructions. This sensitivity can result in a CPU hang scenario.
787 The software must insert either a Data Synchronization Barrier (DSB)
788 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
791 config ARM_ERRATA_326103
792 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
795 Executing a SWP instruction to read-only memory does not set bit 11
796 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
797 treat the access as a read, preventing a COW from occurring and
798 causing the faulting task to livelock.
800 config ARM_ERRATA_411920
801 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
802 depends on CPU_V6 || CPU_V6K
804 Invalidation of the Instruction Cache operation can
805 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
806 It does not affect the MPCore. This option enables the ARM Ltd.
807 recommended workaround.
809 config ARM_ERRATA_430973
810 bool "ARM errata: Stale prediction on replaced interworking branch"
813 This option enables the workaround for the 430973 Cortex-A8
814 r1p* erratum. If a code sequence containing an ARM/Thumb
815 interworking branch is replaced with another code sequence at the
816 same virtual address, whether due to self-modifying code or virtual
817 to physical address re-mapping, Cortex-A8 does not recover from the
818 stale interworking branch prediction. This results in Cortex-A8
819 executing the new code sequence in the incorrect ARM or Thumb state.
820 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
821 and also flushes the branch target cache at every context switch.
822 Note that setting specific bits in the ACTLR register may not be
823 available in non-secure mode.
825 config ARM_ERRATA_458693
826 bool "ARM errata: Processor deadlock when a false hazard is created"
828 depends on !ARCH_MULTIPLATFORM
830 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
831 erratum. For very specific sequences of memory operations, it is
832 possible for a hazard condition intended for a cache line to instead
833 be incorrectly associated with a different cache line. This false
834 hazard might then cause a processor deadlock. The workaround enables
835 the L1 caching of the NEON accesses and disables the PLD instruction
836 in the ACTLR register. Note that setting specific bits in the ACTLR
837 register may not be available in non-secure mode.
839 config ARM_ERRATA_460075
840 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
842 depends on !ARCH_MULTIPLATFORM
844 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
845 erratum. Any asynchronous access to the L2 cache may encounter a
846 situation in which recent store transactions to the L2 cache are lost
847 and overwritten with stale memory contents from external memory. The
848 workaround disables the write-allocate mode for the L2 cache via the
849 ACTLR register. Note that setting specific bits in the ACTLR register
850 may not be available in non-secure mode.
852 config ARM_ERRATA_742230
853 bool "ARM errata: DMB operation may be faulty"
854 depends on CPU_V7 && SMP
855 depends on !ARCH_MULTIPLATFORM
857 This option enables the workaround for the 742230 Cortex-A9
858 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
859 between two write operations may not ensure the correct visibility
860 ordering of the two writes. This workaround sets a specific bit in
861 the diagnostic register of the Cortex-A9 which causes the DMB
862 instruction to behave as a DSB, ensuring the correct behaviour of
865 config ARM_ERRATA_742231
866 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
867 depends on CPU_V7 && SMP
868 depends on !ARCH_MULTIPLATFORM
870 This option enables the workaround for the 742231 Cortex-A9
871 (r2p0..r2p2) erratum. Under certain conditions, specific to the
872 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
873 accessing some data located in the same cache line, may get corrupted
874 data due to bad handling of the address hazard when the line gets
875 replaced from one of the CPUs at the same time as another CPU is
876 accessing it. This workaround sets specific bits in the diagnostic
877 register of the Cortex-A9 which reduces the linefill issuing
878 capabilities of the processor.
880 config ARM_ERRATA_643719
881 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
882 depends on CPU_V7 && SMP
885 This option enables the workaround for the 643719 Cortex-A9 (prior to
886 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
887 register returns zero when it should return one. The workaround
888 corrects this value, ensuring cache maintenance operations which use
889 it behave as intended and avoiding data corruption.
891 config ARM_ERRATA_720789
892 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
895 This option enables the workaround for the 720789 Cortex-A9 (prior to
896 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
897 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
898 As a consequence of this erratum, some TLB entries which should be
899 invalidated are not, resulting in an incoherency in the system page
900 tables. The workaround changes the TLB flushing routines to invalidate
901 entries regardless of the ASID.
903 config ARM_ERRATA_743622
904 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
906 depends on !ARCH_MULTIPLATFORM
908 This option enables the workaround for the 743622 Cortex-A9
909 (r2p*) erratum. Under very rare conditions, a faulty
910 optimisation in the Cortex-A9 Store Buffer may lead to data
911 corruption. This workaround sets a specific bit in the diagnostic
912 register of the Cortex-A9 which disables the Store Buffer
913 optimisation, preventing the defect from occurring. This has no
914 visible impact on the overall performance or power consumption of the
917 config ARM_ERRATA_751472
918 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
920 depends on !ARCH_MULTIPLATFORM
922 This option enables the workaround for the 751472 Cortex-A9 (prior
923 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
924 completion of a following broadcasted operation if the second
925 operation is received by a CPU before the ICIALLUIS has completed,
926 potentially leading to corrupted entries in the cache or TLB.
928 config ARM_ERRATA_754322
929 bool "ARM errata: possible faulty MMU translations following an ASID switch"
932 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
933 r3p*) erratum. A speculative memory access may cause a page table walk
934 which starts prior to an ASID switch but completes afterwards. This
935 can populate the micro-TLB with a stale entry which may be hit with
936 the new ASID. This workaround places two dsb instructions in the mm
937 switching code so that no page table walks can cross the ASID switch.
939 config ARM_ERRATA_754327
940 bool "ARM errata: no automatic Store Buffer drain"
941 depends on CPU_V7 && SMP
943 This option enables the workaround for the 754327 Cortex-A9 (prior to
944 r2p0) erratum. The Store Buffer does not have any automatic draining
945 mechanism and therefore a livelock may occur if an external agent
946 continuously polls a memory location waiting to observe an update.
947 This workaround defines cpu_relax() as smp_mb(), preventing correctly
948 written polling loops from denying visibility of updates to memory.
950 config ARM_ERRATA_364296
951 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
954 This options enables the workaround for the 364296 ARM1136
955 r0p2 erratum (possible cache data corruption with
956 hit-under-miss enabled). It sets the undocumented bit 31 in
957 the auxiliary control register and the FI bit in the control
958 register, thus disabling hit-under-miss without putting the
959 processor into full low interrupt latency mode. ARM11MPCore
962 config ARM_ERRATA_764369
963 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
964 depends on CPU_V7 && SMP
966 This option enables the workaround for erratum 764369
967 affecting Cortex-A9 MPCore with two or more processors (all
968 current revisions). Under certain timing circumstances, a data
969 cache line maintenance operation by MVA targeting an Inner
970 Shareable memory region may fail to proceed up to either the
971 Point of Coherency or to the Point of Unification of the
972 system. This workaround adds a DSB instruction before the
973 relevant cache maintenance functions and sets a specific bit
974 in the diagnostic control register of the SCU.
976 config ARM_ERRATA_775420
977 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
980 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
981 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
982 operation aborts with MMU exception, it might cause the processor
983 to deadlock. This workaround puts DSB before executing ISB if
984 an abort may occur on cache maintenance.
986 config ARM_ERRATA_798181
987 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
988 depends on CPU_V7 && SMP
990 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
991 adequately shooting down all use of the old entries. This
992 option enables the Linux kernel workaround for this erratum
993 which sends an IPI to the CPUs that are running the same ASID
994 as the one being invalidated.
996 config ARM_ERRATA_773022
997 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1000 This option enables the workaround for the 773022 Cortex-A15
1001 (up to r0p4) erratum. In certain rare sequences of code, the
1002 loop buffer may deliver incorrect instructions. This
1003 workaround disables the loop buffer to avoid the erratum.
1005 config ARM_ERRATA_818325_852422
1006 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1009 This option enables the workaround for:
1010 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1011 instruction might deadlock. Fixed in r0p1.
1012 - Cortex-A12 852422: Execution of a sequence of instructions might
1013 lead to either a data corruption or a CPU deadlock. Not fixed in
1014 any Cortex-A12 cores yet.
1015 This workaround for all both errata involves setting bit[12] of the
1016 Feature Register. This bit disables an optimisation applied to a
1017 sequence of 2 instructions that use opposing condition codes.
1019 config ARM_ERRATA_821420
1020 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1023 This option enables the workaround for the 821420 Cortex-A12
1024 (all revs) erratum. In very rare timing conditions, a sequence
1025 of VMOV to Core registers instructions, for which the second
1026 one is in the shadow of a branch or abort, can lead to a
1027 deadlock when the VMOV instructions are issued out-of-order.
1029 config ARM_ERRATA_825619
1030 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1033 This option enables the workaround for the 825619 Cortex-A12
1034 (all revs) erratum. Within rare timing constraints, executing a
1035 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1036 and Device/Strongly-Ordered loads and stores might cause deadlock
1038 config ARM_ERRATA_857271
1039 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1042 This option enables the workaround for the 857271 Cortex-A12
1043 (all revs) erratum. Under very rare timing conditions, the CPU might
1044 hang. The workaround is expected to have a < 1% performance impact.
1046 config ARM_ERRATA_852421
1047 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1050 This option enables the workaround for the 852421 Cortex-A17
1051 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1052 execution of a DMB ST instruction might fail to properly order
1053 stores from GroupA and stores from GroupB.
1055 config ARM_ERRATA_852423
1056 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1059 This option enables the workaround for:
1060 - Cortex-A17 852423: Execution of a sequence of instructions might
1061 lead to either a data corruption or a CPU deadlock. Not fixed in
1062 any Cortex-A17 cores yet.
1063 This is identical to Cortex-A12 erratum 852422. It is a separate
1064 config option from the A12 erratum due to the way errata are checked
1067 config ARM_ERRATA_857272
1068 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1071 This option enables the workaround for the 857272 Cortex-A17 erratum.
1072 This erratum is not known to be fixed in any A17 revision.
1073 This is identical to Cortex-A12 erratum 857271. It is a separate
1074 config option from the A12 erratum due to the way errata are checked
1079 source "arch/arm/common/Kconfig"
1086 Find out whether you have ISA slots on your motherboard. ISA is the
1087 name of a bus system, i.e. the way the CPU talks to the other stuff
1088 inside your box. Other bus systems are PCI, EISA, MicroChannel
1089 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1090 newer boards don't support it. If you have ISA, say Y, otherwise N.
1092 # Select ISA DMA controller support
1097 # Select ISA DMA interface
1101 config PCI_NANOENGINE
1102 bool "BSE nanoEngine PCI support"
1103 depends on SA1100_NANOENGINE
1105 Enable PCI on the BSE nanoEngine board.
1107 config ARM_ERRATA_814220
1108 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1111 The v7 ARM states that all cache and branch predictor maintenance
1112 operations that do not specify an address execute, relative to
1113 each other, in program order.
1114 However, because of this erratum, an L2 set/way cache maintenance
1115 operation can overtake an L1 set/way cache maintenance operation.
1116 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1121 menu "Kernel Features"
1126 This option should be selected by machines which have an SMP-
1129 The only effect of this option is to make the SMP-related
1130 options available to the user for configuration.
1133 bool "Symmetric Multi-Processing"
1134 depends on CPU_V6K || CPU_V7
1136 depends on MMU || ARM_MPU
1139 This enables support for systems with more than one CPU. If you have
1140 a system with only one CPU, say N. If you have a system with more
1141 than one CPU, say Y.
1143 If you say N here, the kernel will run on uni- and multiprocessor
1144 machines, but will use only one CPU of a multiprocessor machine. If
1145 you say Y here, the kernel will run on many, but not all,
1146 uniprocessor machines. On a uniprocessor machine, the kernel
1147 will run faster if you say N here.
1149 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1150 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1151 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1153 If you don't know what to do here, say N.
1156 bool "Allow booting SMP kernel on uniprocessor systems"
1157 depends on SMP && !XIP_KERNEL && MMU
1160 SMP kernels contain instructions which fail on non-SMP processors.
1161 Enabling this option allows the kernel to modify itself to make
1162 these instructions safe. Disabling it allows about 1K of space
1165 If you don't know what to do here, say Y.
1168 config CURRENT_POINTER_IN_TPIDRURO
1170 depends on CPU_32v6K && !CPU_V6
1174 select HAVE_IRQ_EXIT_ON_IRQ_STACK
1175 select HAVE_SOFTIRQ_ON_OWN_STACK
1177 config ARM_CPU_TOPOLOGY
1178 bool "Support cpu topology definition"
1179 depends on SMP && CPU_V7
1182 Support ARM cpu topology definition. The MPIDR register defines
1183 affinity between processors which is then used to describe the cpu
1184 topology of an ARM System.
1187 bool "Multi-core scheduler support"
1188 depends on ARM_CPU_TOPOLOGY
1190 Multi-core scheduler support improves the CPU scheduler's decision
1191 making when dealing with multi-core CPU chips at a cost of slightly
1192 increased overhead in some places. If unsure say N here.
1195 bool "SMT scheduler support"
1196 depends on ARM_CPU_TOPOLOGY
1198 Improves the CPU scheduler's decision making when dealing with
1199 MultiThreading at a cost of slightly increased overhead in some
1200 places. If unsure say N here.
1205 This option enables support for the ARM snoop control unit
1207 config HAVE_ARM_ARCH_TIMER
1208 bool "Architected timer support"
1210 select ARM_ARCH_TIMER
1212 This option enables support for the ARM architected timer
1217 This options enables support for the ARM timer and watchdog unit
1220 bool "Multi-Cluster Power Management"
1221 depends on CPU_V7 && SMP
1223 This option provides the common power management infrastructure
1224 for (multi-)cluster based systems, such as big.LITTLE based
1227 config MCPM_QUAD_CLUSTER
1231 To avoid wasting resources unnecessarily, MCPM only supports up
1232 to 2 clusters by default.
1233 Platforms with 3 or 4 clusters that use MCPM must select this
1234 option to allow the additional clusters to be managed.
1237 bool "big.LITTLE support (Experimental)"
1238 depends on CPU_V7 && SMP
1241 This option enables support selections for the big.LITTLE
1242 system architecture.
1245 bool "big.LITTLE switcher support"
1246 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1249 The big.LITTLE "switcher" provides the core functionality to
1250 transparently handle transition between a cluster of A15's
1251 and a cluster of A7's in a big.LITTLE system.
1253 config BL_SWITCHER_DUMMY_IF
1254 tristate "Simple big.LITTLE switcher user interface"
1255 depends on BL_SWITCHER && DEBUG_KERNEL
1257 This is a simple and dummy char dev interface to control
1258 the big.LITTLE switcher core code. It is meant for
1259 debugging purposes only.
1262 prompt "Memory split"
1266 Select the desired split between kernel and user memory.
1268 If you are not absolutely sure what you are doing, leave this
1272 bool "3G/1G user/kernel split"
1273 config VMSPLIT_3G_OPT
1274 depends on !ARM_LPAE
1275 bool "3G/1G user/kernel split (for full 1G low memory)"
1277 bool "2G/2G user/kernel split"
1279 bool "1G/3G user/kernel split"
1284 default PHYS_OFFSET if !MMU
1285 default 0x40000000 if VMSPLIT_1G
1286 default 0x80000000 if VMSPLIT_2G
1287 default 0xB0000000 if VMSPLIT_3G_OPT
1290 config KASAN_SHADOW_OFFSET
1293 default 0x1f000000 if PAGE_OFFSET=0x40000000
1294 default 0x5f000000 if PAGE_OFFSET=0x80000000
1295 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1296 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1300 int "Maximum number of CPUs (2-32)"
1301 range 2 16 if DEBUG_KMAP_LOCAL
1302 range 2 32 if !DEBUG_KMAP_LOCAL
1306 The maximum number of CPUs that the kernel can support.
1307 Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1308 debugging is enabled, which uses half of the per-CPU fixmap
1309 slots as guard regions.
1312 bool "Support for hot-pluggable CPUs"
1314 select GENERIC_IRQ_MIGRATION
1316 Say Y here to experiment with turning CPUs off and on. CPUs
1317 can be controlled through /sys/devices/system/cpu.
1320 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1321 depends on HAVE_ARM_SMCCC
1324 Say Y here if you want Linux to communicate with system firmware
1325 implementing the PSCI specification for CPU-centric power
1326 management operations described in ARM document number ARM DEN
1327 0022A ("Power State Coordination Interface System Software on
1330 # The GPIO number here must be sorted by descending number. In case of
1331 # a multiplatform kernel, we just want the highest value required by the
1332 # selected platforms.
1335 default 2048 if ARCH_INTEL_SOCFPGA
1336 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1337 ARCH_ZYNQ || ARCH_ASPEED
1338 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1339 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1340 default 416 if ARCH_SUNXI
1341 default 392 if ARCH_U8500
1342 default 352 if ARCH_VT8500
1343 default 288 if ARCH_ROCKCHIP
1344 default 264 if MACH_H4700
1347 Maximum number of GPIOs in the system.
1349 If unsure, leave the default value.
1353 default 128 if SOC_AT91RM9200
1357 depends on HZ_FIXED = 0
1358 prompt "Timer frequency"
1382 default HZ_FIXED if HZ_FIXED != 0
1383 default 100 if HZ_100
1384 default 200 if HZ_200
1385 default 250 if HZ_250
1386 default 300 if HZ_300
1387 default 500 if HZ_500
1391 def_bool HIGH_RES_TIMERS
1393 config THUMB2_KERNEL
1394 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1395 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1396 default y if CPU_THUMBONLY
1399 By enabling this option, the kernel will be compiled in
1404 config ARM_PATCH_IDIV
1405 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1406 depends on CPU_32v7 && !XIP_KERNEL
1409 The ARM compiler inserts calls to __aeabi_idiv() and
1410 __aeabi_uidiv() when it needs to perform division on signed
1411 and unsigned integers. Some v7 CPUs have support for the sdiv
1412 and udiv instructions that can be used to implement those
1415 Enabling this option allows the kernel to modify itself to
1416 replace the first two instructions of these library functions
1417 with the sdiv or udiv plus "bx lr" instructions when the CPU
1418 it is running on supports them. Typically this will be faster
1419 and less power intensive than running the original library
1420 code to do integer division.
1423 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1424 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1425 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1427 This option allows for the kernel to be compiled using the latest
1428 ARM ABI (aka EABI). This is only useful if you are using a user
1429 space environment that is also compiled with EABI.
1431 Since there are major incompatibilities between the legacy ABI and
1432 EABI, especially with regard to structure member alignment, this
1433 option also changes the kernel syscall calling convention to
1434 disambiguate both ABIs and allow for backward compatibility support
1435 (selected with CONFIG_OABI_COMPAT).
1437 To use this you need GCC version 4.0.0 or later.
1440 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1441 depends on AEABI && !THUMB2_KERNEL
1443 This option preserves the old syscall interface along with the
1444 new (ARM EABI) one. It also provides a compatibility layer to
1445 intercept syscalls that have structure arguments which layout
1446 in memory differs between the legacy ABI and the new ARM EABI
1447 (only for non "thumb" binaries). This option adds a tiny
1448 overhead to all syscalls and produces a slightly larger kernel.
1450 The seccomp filter system will not be available when this is
1451 selected, since there is no way yet to sensibly distinguish
1452 between calling conventions during filtering.
1454 If you know you'll be using only pure EABI user space then you
1455 can say N here. If this option is not selected and you attempt
1456 to execute a legacy ABI binary then the result will be
1457 UNPREDICTABLE (in fact it can be predicted that it won't work
1458 at all). If in doubt say N.
1460 config ARCH_SELECT_MEMORY_MODEL
1463 config ARCH_FLATMEM_ENABLE
1466 config ARCH_SPARSEMEM_ENABLE
1468 select SPARSEMEM_STATIC if SPARSEMEM
1471 bool "High Memory Support"
1474 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY
1476 The address space of ARM processors is only 4 Gigabytes large
1477 and it has to accommodate user address space, kernel address
1478 space as well as some memory mapped IO. That means that, if you
1479 have a large amount of physical memory and/or IO, not all of the
1480 memory can be "permanently mapped" by the kernel. The physical
1481 memory that is not permanently mapped is called "high memory".
1483 Depending on the selected kernel/user memory split, minimum
1484 vmalloc space and actual amount of RAM, you may not need this
1485 option which should result in a slightly faster kernel.
1490 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1494 The VM uses one page of physical memory for each page table.
1495 For systems with a lot of processes, this can use a lot of
1496 precious low memory, eventually leading to low memory being
1497 consumed by page tables. Setting this option will allow
1498 user-space 2nd level page tables to reside in high memory.
1500 config CPU_SW_DOMAIN_PAN
1501 bool "Enable use of CPU domains to implement privileged no-access"
1502 depends on MMU && !ARM_LPAE
1505 Increase kernel security by ensuring that normal kernel accesses
1506 are unable to access userspace addresses. This can help prevent
1507 use-after-free bugs becoming an exploitable privilege escalation
1508 by ensuring that magic values (such as LIST_POISON) will always
1509 fault when dereferenced.
1511 CPUs with low-vector mappings use a best-efforts implementation.
1512 Their lower 1MB needs to remain accessible for the vectors, but
1513 the remainder of userspace will become appropriately inaccessible.
1515 config HW_PERF_EVENTS
1519 config ARM_MODULE_PLTS
1520 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1524 Allocate PLTs when loading modules so that jumps and calls whose
1525 targets are too far away for their relative offsets to be encoded
1526 in the instructions themselves can be bounced via veneers in the
1527 module's PLT. This allows modules to be allocated in the generic
1528 vmalloc area after the dedicated module memory area has been
1529 exhausted. The modules will use slightly more memory, but after
1530 rounding up to page size, the actual memory footprint is usually
1533 Disabling this is usually safe for small single-platform
1534 configurations. If unsure, say y.
1536 config FORCE_MAX_ZONEORDER
1537 int "Maximum zone order"
1538 default "12" if SOC_AM33XX
1539 default "9" if SA1111
1542 The kernel memory allocator divides physically contiguous memory
1543 blocks into "zones", where each zone is a power of two number of
1544 pages. This option selects the largest power of two that the kernel
1545 keeps in the memory allocator. If you need to allocate very large
1546 blocks of physically contiguous memory, then you may need to
1547 increase this value.
1549 This config option is actually maximum order plus one. For example,
1550 a value of 11 means that the largest free memory block is 2^10 pages.
1552 config ALIGNMENT_TRAP
1553 def_bool CPU_CP15_MMU
1554 select HAVE_PROC_CPU if PROC_FS
1556 ARM processors cannot fetch/store information which is not
1557 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1558 address divisible by 4. On 32-bit ARM processors, these non-aligned
1559 fetch/store instructions will be emulated in software if you say
1560 here, which has a severe performance impact. This is necessary for
1561 correct operation of some network protocols. With an IP-only
1562 configuration it is safe to say N, otherwise say Y.
1564 config UACCESS_WITH_MEMCPY
1565 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1567 default y if CPU_FEROCEON
1569 Implement faster copy_to_user and clear_user methods for CPU
1570 cores where a 8-word STM instruction give significantly higher
1571 memory write throughput than a sequence of individual 32bit stores.
1573 A possible side effect is a slight increase in scheduling latency
1574 between threads sharing the same address space if they invoke
1575 such copy operations with large buffers.
1577 However, if the CPU data cache is using a write-allocate mode,
1578 this option is unlikely to provide any performance gain.
1581 bool "Enable paravirtualization code"
1583 This changes the kernel so it can modify itself when it is run
1584 under a hypervisor, potentially improving performance significantly
1585 over full virtualization.
1587 config PARAVIRT_TIME_ACCOUNTING
1588 bool "Paravirtual steal time accounting"
1591 Select this option to enable fine granularity task steal time
1592 accounting. Time spent executing other tasks in parallel with
1593 the current vCPU is discounted from the vCPU power. To account for
1594 that, there can be a small performance impact.
1596 If in doubt, say N here.
1603 bool "Xen guest support on ARM"
1604 depends on ARM && AEABI && OF
1605 depends on CPU_V7 && !CPU_V6
1606 depends on !GENERIC_ATOMIC64
1608 select ARCH_DMA_ADDR_T_64BIT
1614 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1616 config CC_HAVE_STACKPROTECTOR_TLS
1617 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1619 config STACKPROTECTOR_PER_TASK
1620 bool "Use a unique stack canary value for each task"
1621 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA
1622 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS
1623 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS
1626 Due to the fact that GCC uses an ordinary symbol reference from
1627 which to load the value of the stack canary, this value can only
1628 change at reboot time on SMP systems, and all tasks running in the
1629 kernel's address space are forced to use the same canary value for
1630 the entire duration that the system is up.
1632 Enable this option to switch to a different method that uses a
1633 different canary value for each task.
1640 bool "Flattened Device Tree support"
1644 Include support for flattened device tree machine descriptions.
1647 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1650 This is the traditional way of passing data to the kernel at boot
1651 time. If you are solely relying on the flattened device tree (or
1652 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1653 to remove ATAGS support from your kernel binary. If unsure,
1656 config DEPRECATED_PARAM_STRUCT
1657 bool "Provide old way to pass kernel parameters"
1660 This was deprecated in 2001 and announced to live on for 5 years.
1661 Some old boot loaders still use this way.
1663 # Compressed boot loader in ROM. Yes, we really want to ask about
1664 # TEXT and BSS so we preserve their values in the config files.
1665 config ZBOOT_ROM_TEXT
1666 hex "Compressed ROM boot loader base address"
1669 The physical address at which the ROM-able zImage is to be
1670 placed in the target. Platforms which normally make use of
1671 ROM-able zImage formats normally set this to a suitable
1672 value in their defconfig file.
1674 If ZBOOT_ROM is not enabled, this has no effect.
1676 config ZBOOT_ROM_BSS
1677 hex "Compressed ROM boot loader BSS address"
1680 The base address of an area of read/write memory in the target
1681 for the ROM-able zImage which must be available while the
1682 decompressor is running. It must be large enough to hold the
1683 entire decompressed kernel plus an additional 128 KiB.
1684 Platforms which normally make use of ROM-able zImage formats
1685 normally set this to a suitable value in their defconfig file.
1687 If ZBOOT_ROM is not enabled, this has no effect.
1690 bool "Compressed boot loader in ROM/flash"
1691 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1692 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1694 Say Y here if you intend to execute your compressed kernel image
1695 (zImage) directly from ROM or flash. If unsure, say N.
1697 config ARM_APPENDED_DTB
1698 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1701 With this option, the boot code will look for a device tree binary
1702 (DTB) appended to zImage
1703 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1705 This is meant as a backward compatibility convenience for those
1706 systems with a bootloader that can't be upgraded to accommodate
1707 the documented boot protocol using a device tree.
1709 Beware that there is very little in terms of protection against
1710 this option being confused by leftover garbage in memory that might
1711 look like a DTB header after a reboot if no actual DTB is appended
1712 to zImage. Do not leave this option active in a production kernel
1713 if you don't intend to always append a DTB. Proper passing of the
1714 location into r2 of a bootloader provided DTB is always preferable
1717 config ARM_ATAG_DTB_COMPAT
1718 bool "Supplement the appended DTB with traditional ATAG information"
1719 depends on ARM_APPENDED_DTB
1721 Some old bootloaders can't be updated to a DTB capable one, yet
1722 they provide ATAGs with memory configuration, the ramdisk address,
1723 the kernel cmdline string, etc. Such information is dynamically
1724 provided by the bootloader and can't always be stored in a static
1725 DTB. To allow a device tree enabled kernel to be used with such
1726 bootloaders, this option allows zImage to extract the information
1727 from the ATAG list and store it at run time into the appended DTB.
1730 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1731 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1733 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1734 bool "Use bootloader kernel arguments if available"
1736 Uses the command-line options passed by the boot loader instead of
1737 the device tree bootargs property. If the boot loader doesn't provide
1738 any, the device tree bootargs property will be used.
1740 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1741 bool "Extend with bootloader kernel arguments"
1743 The command-line arguments provided by the boot loader will be
1744 appended to the the device tree bootargs property.
1749 string "Default kernel command string"
1752 On some architectures (e.g. CATS), there is currently no way
1753 for the boot loader to pass arguments to the kernel. For these
1754 architectures, you should supply some command-line options at build
1755 time by entering them here. As a minimum, you should specify the
1756 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1759 prompt "Kernel command line type" if CMDLINE != ""
1760 default CMDLINE_FROM_BOOTLOADER
1763 config CMDLINE_FROM_BOOTLOADER
1764 bool "Use bootloader kernel arguments if available"
1766 Uses the command-line options passed by the boot loader. If
1767 the boot loader doesn't provide any, the default kernel command
1768 string provided in CMDLINE will be used.
1770 config CMDLINE_EXTEND
1771 bool "Extend bootloader kernel arguments"
1773 The command-line arguments provided by the boot loader will be
1774 appended to the default kernel command string.
1776 config CMDLINE_FORCE
1777 bool "Always use the default kernel command string"
1779 Always use the default kernel command string, even if the boot
1780 loader passes other arguments to the kernel.
1781 This is useful if you cannot or don't want to change the
1782 command-line options your boot loader passes to the kernel.
1786 bool "Kernel Execute-In-Place from ROM"
1787 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1789 Execute-In-Place allows the kernel to run from non-volatile storage
1790 directly addressable by the CPU, such as NOR flash. This saves RAM
1791 space since the text section of the kernel is not loaded from flash
1792 to RAM. Read-write sections, such as the data section and stack,
1793 are still copied to RAM. The XIP kernel is not compressed since
1794 it has to run directly from flash, so it will take more space to
1795 store it. The flash address used to link the kernel object files,
1796 and for storing it, is configuration dependent. Therefore, if you
1797 say Y here, you must know the proper physical address where to
1798 store the kernel image depending on your own flash memory usage.
1800 Also note that the make target becomes "make xipImage" rather than
1801 "make zImage" or "make Image". The final kernel binary to put in
1802 ROM memory will be arch/arm/boot/xipImage.
1806 config XIP_PHYS_ADDR
1807 hex "XIP Kernel Physical Location"
1808 depends on XIP_KERNEL
1809 default "0x00080000"
1811 This is the physical address in your flash memory the kernel will
1812 be linked for and stored to. This address is dependent on your
1815 config XIP_DEFLATED_DATA
1816 bool "Store kernel .data section compressed in ROM"
1817 depends on XIP_KERNEL
1820 Before the kernel is actually executed, its .data section has to be
1821 copied to RAM from ROM. This option allows for storing that data
1822 in compressed form and decompressed to RAM rather than merely being
1823 copied, saving some precious ROM space. A possible drawback is a
1824 slightly longer boot delay.
1827 bool "Kexec system call (EXPERIMENTAL)"
1828 depends on (!SMP || PM_SLEEP_SMP)
1832 kexec is a system call that implements the ability to shutdown your
1833 current kernel, and to start another kernel. It is like a reboot
1834 but it is independent of the system firmware. And like a reboot
1835 you can start any kernel with it, not just Linux.
1837 It is an ongoing process to be certain the hardware in a machine
1838 is properly shutdown, so do not be surprised if this code does not
1839 initially work for you.
1842 bool "Export atags in procfs"
1843 depends on ATAGS && KEXEC
1846 Should the atags used to boot the kernel be exported in an "atags"
1847 file in procfs. Useful with kexec.
1850 bool "Build kdump crash kernel (EXPERIMENTAL)"
1852 Generate crash dump after being started by kexec. This should
1853 be normally only set in special crash dump kernels which are
1854 loaded in the main kernel with kexec-tools into a specially
1855 reserved region and then later executed after a crash by
1856 kdump/kexec. The crash dump kernel must be compiled to a
1857 memory address not used by the main kernel
1859 For more details see Documentation/admin-guide/kdump/kdump.rst
1861 config AUTO_ZRELADDR
1862 bool "Auto calculation of the decompressed kernel image address"
1864 ZRELADDR is the physical address where the decompressed kernel
1865 image will be placed. If AUTO_ZRELADDR is selected, the address
1866 will be determined at run-time, either by masking the current IP
1867 with 0xf8000000, or, if invalid, from the DTB passed in r2.
1868 This assumes the zImage being placed in the first 128MB from
1875 bool "UEFI runtime support"
1876 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1878 select EFI_PARAMS_FROM_FDT
1880 select EFI_GENERIC_STUB
1881 select EFI_RUNTIME_WRAPPERS
1883 This option provides support for runtime services provided
1884 by UEFI firmware (such as non-volatile variables, realtime
1885 clock, and platform reset). A UEFI stub is also provided to
1886 allow the kernel to be booted as an EFI application. This
1887 is only useful for kernels that may run on systems that have
1891 bool "Enable support for SMBIOS (DMI) tables"
1895 This enables SMBIOS/DMI feature for systems.
1897 This option is only useful on systems that have UEFI firmware.
1898 However, even with this option, the resultant kernel should
1899 continue to boot on existing non-UEFI platforms.
1901 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1902 i.e., the the practice of identifying the platform via DMI to
1903 decide whether certain workarounds for buggy hardware and/or
1904 firmware need to be enabled. This would require the DMI subsystem
1905 to be enabled much earlier than we do on ARM, which is non-trivial.
1909 menu "CPU Power Management"
1911 source "drivers/cpufreq/Kconfig"
1913 source "drivers/cpuidle/Kconfig"
1917 menu "Floating point emulation"
1919 comment "At least one emulation must be selected"
1922 bool "NWFPE math emulation"
1923 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1925 Say Y to include the NWFPE floating point emulator in the kernel.
1926 This is necessary to run most binaries. Linux does not currently
1927 support floating point hardware so you need to say Y here even if
1928 your machine has an FPA or floating point co-processor podule.
1930 You may say N here if you are going to load the Acorn FPEmulator
1931 early in the bootup.
1934 bool "Support extended precision"
1935 depends on FPE_NWFPE
1937 Say Y to include 80-bit support in the kernel floating-point
1938 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1939 Note that gcc does not generate 80-bit operations by default,
1940 so in most cases this option only enlarges the size of the
1941 floating point emulator without any good reason.
1943 You almost surely want to say N here.
1946 bool "FastFPE math emulation (EXPERIMENTAL)"
1947 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1949 Say Y here to include the FAST floating point emulator in the kernel.
1950 This is an experimental much faster emulator which now also has full
1951 precision for the mantissa. It does not support any exceptions.
1952 It is very simple, and approximately 3-6 times faster than NWFPE.
1954 It should be sufficient for most programs. It may be not suitable
1955 for scientific calculations, but you have to check this for yourself.
1956 If you do not feel you need a faster FP emulation you should better
1960 bool "VFP-format floating point maths"
1961 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1963 Say Y to include VFP support code in the kernel. This is needed
1964 if your hardware includes a VFP unit.
1966 Please see <file:Documentation/arm/vfp/release-notes.rst> for
1967 release notes and additional status information.
1969 Say N if your target does not have VFP hardware.
1977 bool "Advanced SIMD (NEON) Extension support"
1978 depends on VFPv3 && CPU_V7
1980 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1983 config KERNEL_MODE_NEON
1984 bool "Support for NEON in kernel mode"
1985 depends on NEON && AEABI
1987 Say Y to include support for NEON in kernel mode.
1991 menu "Power management options"
1993 source "kernel/power/Kconfig"
1995 config ARCH_SUSPEND_POSSIBLE
1996 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1997 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2000 config ARM_CPU_SUSPEND
2001 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2002 depends on ARCH_SUSPEND_POSSIBLE
2004 config ARCH_HIBERNATION_POSSIBLE
2007 default y if ARCH_SUSPEND_POSSIBLE
2012 source "arch/arm/crypto/Kconfig"
2015 source "arch/arm/Kconfig.assembler"