1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND
7 select ARCH_HAS_BINFMT_FLAT
8 select ARCH_HAS_CPU_FINALIZE_INIT if MMU
9 select ARCH_HAS_CURRENT_STACK_POINTER
10 select ARCH_HAS_DEBUG_VIRTUAL if MMU
11 select ARCH_HAS_DMA_ALLOC if MMU
12 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
13 select ARCH_HAS_ELF_RANDOMIZE
14 select ARCH_HAS_FORTIFY_SOURCE
15 select ARCH_HAS_KEEPINITRD
17 select ARCH_HAS_MEMBARRIER_SYNC_CORE
18 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
19 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
20 select ARCH_HAS_SETUP_DMA_OPS
21 select ARCH_HAS_SET_MEMORY
23 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
24 select ARCH_HAS_STRICT_MODULE_RWX if MMU
25 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
26 select ARCH_HAS_SYNC_DMA_FOR_CPU
27 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
28 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
29 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
30 select ARCH_HAS_GCOV_PROFILE_ALL
31 select ARCH_KEEP_MEMBLOCK
32 select ARCH_HAS_UBSAN_SANITIZE_ALL
33 select ARCH_MIGHT_HAVE_PC_PARPORT
34 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
35 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
36 select ARCH_SUPPORTS_ATOMIC_RMW
37 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
38 select ARCH_USE_BUILTIN_BSWAP
39 select ARCH_USE_CMPXCHG_LOCKREF
40 select ARCH_USE_MEMTEST
41 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
42 select ARCH_WANT_GENERAL_HUGETLB
43 select ARCH_WANT_IPC_PARSE_VERSION
44 select ARCH_WANT_LD_ORPHAN_WARN
45 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
46 select BUILDTIME_TABLE_SORT if MMU
47 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE)
48 select CLONE_BACKWARDS
49 select CPU_PM if SUSPEND || CPU_IDLE
50 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
51 select DMA_DECLARE_COHERENT
52 select DMA_GLOBAL_POOL if !MMU
54 select DMA_NONCOHERENT_MMAP if MMU
56 select EDAC_ATOMIC_SCRUB
57 select GENERIC_ALLOCATOR
58 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
59 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
60 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
61 select GENERIC_IRQ_IPI if SMP
62 select GENERIC_CPU_AUTOPROBE
63 select GENERIC_EARLY_IOREMAP
64 select GENERIC_IDLE_POLL_SETUP
65 select GENERIC_IRQ_MULTI_HANDLER
66 select GENERIC_IRQ_PROBE
67 select GENERIC_IRQ_SHOW
68 select GENERIC_IRQ_SHOW_LEVEL
69 select GENERIC_LIB_DEVMEM_IS_ALLOWED
70 select GENERIC_PCI_IOMAP
71 select GENERIC_SCHED_CLOCK
72 select GENERIC_SMP_IDLE_THREAD
73 select HARDIRQS_SW_RESEND
75 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
76 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
77 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
78 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL
79 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
80 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
81 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
82 select HAVE_ARCH_MMAP_RND_BITS if MMU
83 select HAVE_ARCH_PFN_VALID
84 select HAVE_ARCH_SECCOMP
85 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
86 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
87 select HAVE_ARCH_TRACEHOOK
88 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
89 select HAVE_ARM_SMCCC if CPU_V7
90 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
91 select HAVE_CONTEXT_TRACKING_USER
92 select HAVE_C_RECORDMCOUNT
93 select HAVE_BUILDTIME_MCOUNT_SORT
94 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
95 select HAVE_DMA_CONTIGUOUS if MMU
96 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
97 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
98 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
99 select HAVE_EXIT_THREAD
100 select HAVE_FAST_GUP if ARM_LPAE
101 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
102 select HAVE_FUNCTION_ERROR_INJECTION
103 select HAVE_FUNCTION_GRAPH_TRACER
104 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
105 select HAVE_GCC_PLUGINS
106 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
107 select HAVE_IRQ_TIME_ACCOUNTING
108 select HAVE_KERNEL_GZIP
109 select HAVE_KERNEL_LZ4
110 select HAVE_KERNEL_LZMA
111 select HAVE_KERNEL_LZO
112 select HAVE_KERNEL_XZ
113 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
114 select HAVE_KRETPROBES if HAVE_KPROBES
115 select HAVE_MOD_ARCH_SPECIFIC
117 select HAVE_OPTPROBES if !THUMB2_KERNEL
118 select HAVE_PCI if MMU
119 select HAVE_PERF_EVENTS
120 select HAVE_PERF_REGS
121 select HAVE_PERF_USER_STACK_DUMP
122 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
123 select HAVE_REGS_AND_STACK_ACCESS_API
125 select HAVE_STACKPROTECTOR
126 select HAVE_SYSCALL_TRACEPOINTS
128 select HAVE_VIRT_CPU_ACCOUNTING_GEN
129 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
130 select IRQ_FORCED_THREADING
131 select LOCK_MM_AND_FIND_VMA
132 select MODULES_USE_ELF_REL
133 select NEED_DMA_MAP_STATE
134 select OF_EARLY_FLATTREE if OF
136 select OLD_SIGSUSPEND3
137 select PCI_DOMAINS_GENERIC if PCI
138 select PCI_SYSCALL if PCI
139 select PERF_USE_VMALLOC
141 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC)
142 select SYS_SUPPORTS_APM_EMULATION
143 select THREAD_INFO_IN_TASK
144 select TIMER_OF if OF
145 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS
146 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
147 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
148 # Above selects are sorted alphabetically; please add new ones
149 # according to that. Thanks.
151 The ARM series is a line of low-power-consumption RISC chip designs
152 licensed by ARM Ltd and targeted at embedded applications and
153 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
154 manufactured, but legacy ARM-based PC hardware remains popular in
155 Europe. There is an ARM Linux project with a web page at
156 <http://www.arm.linux.org.uk/>.
158 config ARM_HAS_GROUP_RELOCS
160 depends on !LD_IS_LLD || LLD_VERSION >= 140000
161 depends on !COMPILE_TEST
163 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group
164 relocations, which have been around for a long time, but were not
165 supported in LLD until version 14. The combined range is -/+ 256 MiB,
166 which is usually sufficient, but not for allyesconfig, so we disable
167 this feature when doing compile testing.
169 config ARM_DMA_USE_IOMMU
171 select NEED_SG_DMA_LENGTH
175 config ARM_DMA_IOMMU_ALIGNMENT
176 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
180 DMA mapping framework by default aligns all buffers to the smallest
181 PAGE_SIZE order which is greater than or equal to the requested buffer
182 size. This works well for buffers up to a few hundreds kilobytes, but
183 for larger buffers it just a waste of address space. Drivers which has
184 relatively small addressing window (like 64Mib) might run out of
185 virtual space with just a few allocations.
187 With this parameter you can specify the maximum PAGE_SIZE order for
188 DMA IOMMU buffers. Larger buffers will be aligned only to this
189 specified order. The order is expressed as a power of two multiplied
194 config SYS_SUPPORTS_APM_EMULATION
199 select GENERIC_ALLOCATOR
210 config STACKTRACE_SUPPORT
214 config LOCKDEP_SUPPORT
218 config ARCH_HAS_ILOG2_U32
221 config ARCH_HAS_ILOG2_U64
224 config ARCH_HAS_BANDGAP
227 config FIX_EARLYCON_MEM
230 config GENERIC_HWEIGHT
234 config GENERIC_CALIBRATE_DELAY
238 config ARCH_MAY_HAVE_PC_FDC
241 config ARCH_SUPPORTS_UPROBES
244 config GENERIC_ISA_DMA
253 config ARM_PATCH_PHYS_VIRT
254 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM
258 Patch phys-to-virt and virt-to-phys translation functions at
259 boot and module load time according to the position of the
260 kernel in system memory.
262 This can only be used with non-XIP MMU kernels where the base
263 of physical memory is at a 2 MiB boundary.
265 Only disable this option if you know that you do not require
266 this feature (eg, building a kernel for a single machine) and
267 you need to shrink the kernel to the minimal size.
269 config NEED_MACH_IO_H
272 Select this when mach/io.h is required to provide special
273 definitions for this platform. The need for mach/io.h should
274 be avoided when possible.
276 config NEED_MACH_MEMORY_H
279 Select this when mach/memory.h is required to provide special
280 definitions for this platform. The need for mach/memory.h should
281 be avoided when possible.
284 hex "Physical address of main memory" if MMU
285 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR
286 default DRAM_BASE if !MMU
287 default 0x00000000 if ARCH_FOOTBRIDGE
288 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
289 default 0xa0000000 if ARCH_PXA
290 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
293 Please provide the physical address corresponding to the
294 location of main memory in your system.
300 config PGTABLE_LEVELS
302 default 3 if ARM_LPAE
308 bool "MMU-based Paged Memory Management Support"
311 Select if you want MMU-based virtualised addressing space
312 support by paged memory management. If unsure, say 'Y'.
314 config ARM_SINGLE_ARMV7M
320 config ARCH_MMAP_RND_BITS_MIN
323 config ARCH_MMAP_RND_BITS_MAX
324 default 14 if PAGE_OFFSET=0x40000000
325 default 15 if PAGE_OFFSET=0x80000000
328 config ARCH_MULTIPLATFORM
329 bool "Require kernel to be portable to multiple machines" if EXPERT
330 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
333 In general, all Arm machines can be supported in a single
334 kernel image, covering either Armv4/v5 or Armv6/v7.
336 However, some configuration options require hardcoding machine
337 specific physical addresses or enable errata workarounds that may
338 break other machines.
340 Selecting N here allows using those options, including
341 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y.
343 source "arch/arm/Kconfig.platforms"
346 bool "Airoha SoC Support"
347 depends on ARCH_MULTI_V7
352 select HAVE_ARM_ARCH_TIMER
354 Support for Airoha EN7523 SoCs
357 # This is sorted alphabetically by mach-* pathname. However, plat-*
358 # Kconfigs may be included either alphabetically (according to the
359 # plat- suffix) or along side the corresponding mach-* source.
361 source "arch/arm/mach-actions/Kconfig"
363 source "arch/arm/mach-alpine/Kconfig"
365 source "arch/arm/mach-artpec/Kconfig"
367 source "arch/arm/mach-aspeed/Kconfig"
369 source "arch/arm/mach-at91/Kconfig"
371 source "arch/arm/mach-axxia/Kconfig"
373 source "arch/arm/mach-bcm/Kconfig"
375 source "arch/arm/mach-berlin/Kconfig"
377 source "arch/arm/mach-clps711x/Kconfig"
379 source "arch/arm/mach-davinci/Kconfig"
381 source "arch/arm/mach-digicolor/Kconfig"
383 source "arch/arm/mach-dove/Kconfig"
385 source "arch/arm/mach-ep93xx/Kconfig"
387 source "arch/arm/mach-exynos/Kconfig"
389 source "arch/arm/mach-footbridge/Kconfig"
391 source "arch/arm/mach-gemini/Kconfig"
393 source "arch/arm/mach-highbank/Kconfig"
395 source "arch/arm/mach-hisi/Kconfig"
397 source "arch/arm/mach-hpe/Kconfig"
399 source "arch/arm/mach-imx/Kconfig"
401 source "arch/arm/mach-ixp4xx/Kconfig"
403 source "arch/arm/mach-keystone/Kconfig"
405 source "arch/arm/mach-lpc32xx/Kconfig"
407 source "arch/arm/mach-mediatek/Kconfig"
409 source "arch/arm/mach-meson/Kconfig"
411 source "arch/arm/mach-milbeaut/Kconfig"
413 source "arch/arm/mach-mmp/Kconfig"
415 source "arch/arm/mach-moxart/Kconfig"
417 source "arch/arm/mach-mstar/Kconfig"
419 source "arch/arm/mach-mv78xx0/Kconfig"
421 source "arch/arm/mach-mvebu/Kconfig"
423 source "arch/arm/mach-mxs/Kconfig"
425 source "arch/arm/mach-nomadik/Kconfig"
427 source "arch/arm/mach-npcm/Kconfig"
429 source "arch/arm/mach-nspire/Kconfig"
431 source "arch/arm/mach-omap1/Kconfig"
433 source "arch/arm/mach-omap2/Kconfig"
435 source "arch/arm/mach-orion5x/Kconfig"
437 source "arch/arm/mach-pxa/Kconfig"
439 source "arch/arm/mach-qcom/Kconfig"
441 source "arch/arm/mach-rda/Kconfig"
443 source "arch/arm/mach-realtek/Kconfig"
445 source "arch/arm/mach-rpc/Kconfig"
447 source "arch/arm/mach-rockchip/Kconfig"
449 source "arch/arm/mach-s3c/Kconfig"
451 source "arch/arm/mach-s5pv210/Kconfig"
453 source "arch/arm/mach-sa1100/Kconfig"
455 source "arch/arm/mach-shmobile/Kconfig"
457 source "arch/arm/mach-socfpga/Kconfig"
459 source "arch/arm/mach-spear/Kconfig"
461 source "arch/arm/mach-sti/Kconfig"
463 source "arch/arm/mach-stm32/Kconfig"
465 source "arch/arm/mach-sunplus/Kconfig"
467 source "arch/arm/mach-sunxi/Kconfig"
469 source "arch/arm/mach-tegra/Kconfig"
471 source "arch/arm/mach-uniphier/Kconfig"
473 source "arch/arm/mach-ux500/Kconfig"
475 source "arch/arm/mach-versatile/Kconfig"
477 source "arch/arm/mach-vt8500/Kconfig"
479 source "arch/arm/mach-zynq/Kconfig"
481 # ARMv7-M architecture
483 bool "NXP LPC18xx/LPC43xx"
484 depends on ARM_SINGLE_ARMV7M
485 select ARCH_HAS_RESET_CONTROLLER
487 select CLKSRC_LPC32XX
490 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
491 high performance microcontrollers.
494 bool "ARM MPS2 platform"
495 depends on ARM_SINGLE_ARMV7M
499 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
500 with a range of available cores like Cortex-M3/M4/M7.
502 Please, note that depends which Application Note is used memory map
503 for the platform may vary, so adjustment of RAM base might be needed.
505 # Definitions to make life easier
512 select GENERIC_IRQ_CHIP
515 config PLAT_ORION_LEGACY
519 config PLAT_VERSATILE
522 source "arch/arm/mm/Kconfig"
525 bool "Enable iWMMXt support"
526 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
527 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
529 Enable support for iWMMXt context switching at run time if
530 running on a CPU that supports it.
533 source "arch/arm/Kconfig-nommu"
536 config PJ4B_ERRATA_4742
537 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
538 depends on CPU_PJ4B && MACH_ARMADA_370
541 When coming out of either a Wait for Interrupt (WFI) or a Wait for
542 Event (WFE) IDLE states, a specific timing sensitivity exists between
543 the retiring WFI/WFE instructions and the newly issued subsequent
544 instructions. This sensitivity can result in a CPU hang scenario.
546 The software must insert either a Data Synchronization Barrier (DSB)
547 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
550 config ARM_ERRATA_326103
551 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
554 Executing a SWP instruction to read-only memory does not set bit 11
555 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
556 treat the access as a read, preventing a COW from occurring and
557 causing the faulting task to livelock.
559 config ARM_ERRATA_411920
560 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
561 depends on CPU_V6 || CPU_V6K
563 Invalidation of the Instruction Cache operation can
564 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
565 It does not affect the MPCore. This option enables the ARM Ltd.
566 recommended workaround.
568 config ARM_ERRATA_430973
569 bool "ARM errata: Stale prediction on replaced interworking branch"
572 This option enables the workaround for the 430973 Cortex-A8
573 r1p* erratum. If a code sequence containing an ARM/Thumb
574 interworking branch is replaced with another code sequence at the
575 same virtual address, whether due to self-modifying code or virtual
576 to physical address re-mapping, Cortex-A8 does not recover from the
577 stale interworking branch prediction. This results in Cortex-A8
578 executing the new code sequence in the incorrect ARM or Thumb state.
579 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
580 and also flushes the branch target cache at every context switch.
581 Note that setting specific bits in the ACTLR register may not be
582 available in non-secure mode.
584 config ARM_ERRATA_458693
585 bool "ARM errata: Processor deadlock when a false hazard is created"
587 depends on !ARCH_MULTIPLATFORM
589 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
590 erratum. For very specific sequences of memory operations, it is
591 possible for a hazard condition intended for a cache line to instead
592 be incorrectly associated with a different cache line. This false
593 hazard might then cause a processor deadlock. The workaround enables
594 the L1 caching of the NEON accesses and disables the PLD instruction
595 in the ACTLR register. Note that setting specific bits in the ACTLR
596 register may not be available in non-secure mode and thus is not
597 available on a multiplatform kernel. This should be applied by the
600 config ARM_ERRATA_460075
601 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
603 depends on !ARCH_MULTIPLATFORM
605 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
606 erratum. Any asynchronous access to the L2 cache may encounter a
607 situation in which recent store transactions to the L2 cache are lost
608 and overwritten with stale memory contents from external memory. The
609 workaround disables the write-allocate mode for the L2 cache via the
610 ACTLR register. Note that setting specific bits in the ACTLR register
611 may not be available in non-secure mode and thus is not available on
612 a multiplatform kernel. This should be applied by the bootloader
615 config ARM_ERRATA_742230
616 bool "ARM errata: DMB operation may be faulty"
617 depends on CPU_V7 && SMP
618 depends on !ARCH_MULTIPLATFORM
620 This option enables the workaround for the 742230 Cortex-A9
621 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
622 between two write operations may not ensure the correct visibility
623 ordering of the two writes. This workaround sets a specific bit in
624 the diagnostic register of the Cortex-A9 which causes the DMB
625 instruction to behave as a DSB, ensuring the correct behaviour of
626 the two writes. Note that setting specific bits in the diagnostics
627 register may not be available in non-secure mode and thus is not
628 available on a multiplatform kernel. This should be applied by the
631 config ARM_ERRATA_742231
632 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
633 depends on CPU_V7 && SMP
634 depends on !ARCH_MULTIPLATFORM
636 This option enables the workaround for the 742231 Cortex-A9
637 (r2p0..r2p2) erratum. Under certain conditions, specific to the
638 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
639 accessing some data located in the same cache line, may get corrupted
640 data due to bad handling of the address hazard when the line gets
641 replaced from one of the CPUs at the same time as another CPU is
642 accessing it. This workaround sets specific bits in the diagnostic
643 register of the Cortex-A9 which reduces the linefill issuing
644 capabilities of the processor. Note that setting specific bits in the
645 diagnostics register may not be available in non-secure mode and thus
646 is not available on a multiplatform kernel. This should be applied by
647 the bootloader instead.
649 config ARM_ERRATA_643719
650 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
651 depends on CPU_V7 && SMP
654 This option enables the workaround for the 643719 Cortex-A9 (prior to
655 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
656 register returns zero when it should return one. The workaround
657 corrects this value, ensuring cache maintenance operations which use
658 it behave as intended and avoiding data corruption.
660 config ARM_ERRATA_720789
661 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
664 This option enables the workaround for the 720789 Cortex-A9 (prior to
665 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
666 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
667 As a consequence of this erratum, some TLB entries which should be
668 invalidated are not, resulting in an incoherency in the system page
669 tables. The workaround changes the TLB flushing routines to invalidate
670 entries regardless of the ASID.
672 config ARM_ERRATA_743622
673 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
675 depends on !ARCH_MULTIPLATFORM
677 This option enables the workaround for the 743622 Cortex-A9
678 (r2p*) erratum. Under very rare conditions, a faulty
679 optimisation in the Cortex-A9 Store Buffer may lead to data
680 corruption. This workaround sets a specific bit in the diagnostic
681 register of the Cortex-A9 which disables the Store Buffer
682 optimisation, preventing the defect from occurring. This has no
683 visible impact on the overall performance or power consumption of the
684 processor. Note that setting specific bits in the diagnostics register
685 may not be available in non-secure mode and thus is not available on a
686 multiplatform kernel. This should be applied by the bootloader instead.
688 config ARM_ERRATA_751472
689 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
691 depends on !ARCH_MULTIPLATFORM
693 This option enables the workaround for the 751472 Cortex-A9 (prior
694 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
695 completion of a following broadcasted operation if the second
696 operation is received by a CPU before the ICIALLUIS has completed,
697 potentially leading to corrupted entries in the cache or TLB.
698 Note that setting specific bits in the diagnostics register may
699 not be available in non-secure mode and thus is not available on
700 a multiplatform kernel. This should be applied by the bootloader
703 config ARM_ERRATA_754322
704 bool "ARM errata: possible faulty MMU translations following an ASID switch"
707 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
708 r3p*) erratum. A speculative memory access may cause a page table walk
709 which starts prior to an ASID switch but completes afterwards. This
710 can populate the micro-TLB with a stale entry which may be hit with
711 the new ASID. This workaround places two dsb instructions in the mm
712 switching code so that no page table walks can cross the ASID switch.
714 config ARM_ERRATA_754327
715 bool "ARM errata: no automatic Store Buffer drain"
716 depends on CPU_V7 && SMP
718 This option enables the workaround for the 754327 Cortex-A9 (prior to
719 r2p0) erratum. The Store Buffer does not have any automatic draining
720 mechanism and therefore a livelock may occur if an external agent
721 continuously polls a memory location waiting to observe an update.
722 This workaround defines cpu_relax() as smp_mb(), preventing correctly
723 written polling loops from denying visibility of updates to memory.
725 config ARM_ERRATA_364296
726 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
729 This options enables the workaround for the 364296 ARM1136
730 r0p2 erratum (possible cache data corruption with
731 hit-under-miss enabled). It sets the undocumented bit 31 in
732 the auxiliary control register and the FI bit in the control
733 register, thus disabling hit-under-miss without putting the
734 processor into full low interrupt latency mode. ARM11MPCore
737 config ARM_ERRATA_764369
738 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
739 depends on CPU_V7 && SMP
741 This option enables the workaround for erratum 764369
742 affecting Cortex-A9 MPCore with two or more processors (all
743 current revisions). Under certain timing circumstances, a data
744 cache line maintenance operation by MVA targeting an Inner
745 Shareable memory region may fail to proceed up to either the
746 Point of Coherency or to the Point of Unification of the
747 system. This workaround adds a DSB instruction before the
748 relevant cache maintenance functions and sets a specific bit
749 in the diagnostic control register of the SCU.
751 config ARM_ERRATA_764319
752 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"
755 This option enables the workaround for the 764319 Cortex A-9 erratum.
756 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an
757 unexpected Undefined Instruction exception when the DBGSWENABLE
758 external pin is set to 0, even when the CP14 accesses are performed
759 from a privileged mode. This work around catches the exception in a
760 way the kernel does not stop execution.
762 config ARM_ERRATA_775420
763 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
766 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
767 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
768 operation aborts with MMU exception, it might cause the processor
769 to deadlock. This workaround puts DSB before executing ISB if
770 an abort may occur on cache maintenance.
772 config ARM_ERRATA_798181
773 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
774 depends on CPU_V7 && SMP
776 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
777 adequately shooting down all use of the old entries. This
778 option enables the Linux kernel workaround for this erratum
779 which sends an IPI to the CPUs that are running the same ASID
780 as the one being invalidated.
782 config ARM_ERRATA_773022
783 bool "ARM errata: incorrect instructions may be executed from loop buffer"
786 This option enables the workaround for the 773022 Cortex-A15
787 (up to r0p4) erratum. In certain rare sequences of code, the
788 loop buffer may deliver incorrect instructions. This
789 workaround disables the loop buffer to avoid the erratum.
791 config ARM_ERRATA_818325_852422
792 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
795 This option enables the workaround for:
796 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
797 instruction might deadlock. Fixed in r0p1.
798 - Cortex-A12 852422: Execution of a sequence of instructions might
799 lead to either a data corruption or a CPU deadlock. Not fixed in
800 any Cortex-A12 cores yet.
801 This workaround for all both errata involves setting bit[12] of the
802 Feature Register. This bit disables an optimisation applied to a
803 sequence of 2 instructions that use opposing condition codes.
805 config ARM_ERRATA_821420
806 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
809 This option enables the workaround for the 821420 Cortex-A12
810 (all revs) erratum. In very rare timing conditions, a sequence
811 of VMOV to Core registers instructions, for which the second
812 one is in the shadow of a branch or abort, can lead to a
813 deadlock when the VMOV instructions are issued out-of-order.
815 config ARM_ERRATA_825619
816 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
819 This option enables the workaround for the 825619 Cortex-A12
820 (all revs) erratum. Within rare timing constraints, executing a
821 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
822 and Device/Strongly-Ordered loads and stores might cause deadlock
824 config ARM_ERRATA_857271
825 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
828 This option enables the workaround for the 857271 Cortex-A12
829 (all revs) erratum. Under very rare timing conditions, the CPU might
830 hang. The workaround is expected to have a < 1% performance impact.
832 config ARM_ERRATA_852421
833 bool "ARM errata: A17: DMB ST might fail to create order between stores"
836 This option enables the workaround for the 852421 Cortex-A17
837 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
838 execution of a DMB ST instruction might fail to properly order
839 stores from GroupA and stores from GroupB.
841 config ARM_ERRATA_852423
842 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
845 This option enables the workaround for:
846 - Cortex-A17 852423: Execution of a sequence of instructions might
847 lead to either a data corruption or a CPU deadlock. Not fixed in
848 any Cortex-A17 cores yet.
849 This is identical to Cortex-A12 erratum 852422. It is a separate
850 config option from the A12 erratum due to the way errata are checked
853 config ARM_ERRATA_857272
854 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
857 This option enables the workaround for the 857272 Cortex-A17 erratum.
858 This erratum is not known to be fixed in any A17 revision.
859 This is identical to Cortex-A12 erratum 857271. It is a separate
860 config option from the A12 erratum due to the way errata are checked
865 source "arch/arm/common/Kconfig"
872 Find out whether you have ISA slots on your motherboard. ISA is the
873 name of a bus system, i.e. the way the CPU talks to the other stuff
874 inside your box. Other bus systems are PCI, EISA, MicroChannel
875 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
876 newer boards don't support it. If you have ISA, say Y, otherwise N.
878 # Select ISA DMA interface
882 config ARM_ERRATA_814220
883 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
886 The v7 ARM states that all cache and branch predictor maintenance
887 operations that do not specify an address execute, relative to
888 each other, in program order.
889 However, because of this erratum, an L2 set/way cache maintenance
890 operation can overtake an L1 set/way cache maintenance operation.
891 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
896 menu "Kernel Features"
901 This option should be selected by machines which have an SMP-
904 The only effect of this option is to make the SMP-related
905 options available to the user for configuration.
908 bool "Symmetric Multi-Processing"
909 depends on CPU_V6K || CPU_V7
911 depends on MMU || ARM_MPU
914 This enables support for systems with more than one CPU. If you have
915 a system with only one CPU, say N. If you have a system with more
918 If you say N here, the kernel will run on uni- and multiprocessor
919 machines, but will use only one CPU of a multiprocessor machine. If
920 you say Y here, the kernel will run on many, but not all,
921 uniprocessor machines. On a uniprocessor machine, the kernel
922 will run faster if you say N here.
924 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
925 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
926 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
928 If you don't know what to do here, say N.
931 bool "Allow booting SMP kernel on uniprocessor systems"
932 depends on SMP && MMU
935 SMP kernels contain instructions which fail on non-SMP processors.
936 Enabling this option allows the kernel to modify itself to make
937 these instructions safe. Disabling it allows about 1K of space
940 If you don't know what to do here, say Y.
943 config CURRENT_POINTER_IN_TPIDRURO
945 depends on CPU_32v6K && !CPU_V6
949 select HAVE_IRQ_EXIT_ON_IRQ_STACK
950 select HAVE_SOFTIRQ_ON_OWN_STACK
952 config ARM_CPU_TOPOLOGY
953 bool "Support cpu topology definition"
954 depends on SMP && CPU_V7
957 Support ARM cpu topology definition. The MPIDR register defines
958 affinity between processors which is then used to describe the cpu
959 topology of an ARM System.
962 bool "Multi-core scheduler support"
963 depends on ARM_CPU_TOPOLOGY
965 Multi-core scheduler support improves the CPU scheduler's decision
966 making when dealing with multi-core CPU chips at a cost of slightly
967 increased overhead in some places. If unsure say N here.
970 bool "SMT scheduler support"
971 depends on ARM_CPU_TOPOLOGY
973 Improves the CPU scheduler's decision making when dealing with
974 MultiThreading at a cost of slightly increased overhead in some
975 places. If unsure say N here.
980 This option enables support for the ARM snoop control unit
982 config HAVE_ARM_ARCH_TIMER
983 bool "Architected timer support"
985 select ARM_ARCH_TIMER
987 This option enables support for the ARM architected timer
992 This options enables support for the ARM timer and watchdog unit
995 bool "Multi-Cluster Power Management"
996 depends on CPU_V7 && SMP
998 This option provides the common power management infrastructure
999 for (multi-)cluster based systems, such as big.LITTLE based
1002 config MCPM_QUAD_CLUSTER
1006 To avoid wasting resources unnecessarily, MCPM only supports up
1007 to 2 clusters by default.
1008 Platforms with 3 or 4 clusters that use MCPM must select this
1009 option to allow the additional clusters to be managed.
1012 bool "big.LITTLE support (Experimental)"
1013 depends on CPU_V7 && SMP
1016 This option enables support selections for the big.LITTLE
1017 system architecture.
1020 bool "big.LITTLE switcher support"
1021 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1024 The big.LITTLE "switcher" provides the core functionality to
1025 transparently handle transition between a cluster of A15's
1026 and a cluster of A7's in a big.LITTLE system.
1028 config BL_SWITCHER_DUMMY_IF
1029 tristate "Simple big.LITTLE switcher user interface"
1030 depends on BL_SWITCHER && DEBUG_KERNEL
1032 This is a simple and dummy char dev interface to control
1033 the big.LITTLE switcher core code. It is meant for
1034 debugging purposes only.
1037 prompt "Memory split"
1041 Select the desired split between kernel and user memory.
1043 If you are not absolutely sure what you are doing, leave this
1047 bool "3G/1G user/kernel split"
1048 config VMSPLIT_3G_OPT
1049 depends on !ARM_LPAE
1050 bool "3G/1G user/kernel split (for full 1G low memory)"
1052 bool "2G/2G user/kernel split"
1054 bool "1G/3G user/kernel split"
1059 default PHYS_OFFSET if !MMU
1060 default 0x40000000 if VMSPLIT_1G
1061 default 0x80000000 if VMSPLIT_2G
1062 default 0xB0000000 if VMSPLIT_3G_OPT
1065 config KASAN_SHADOW_OFFSET
1068 default 0x1f000000 if PAGE_OFFSET=0x40000000
1069 default 0x5f000000 if PAGE_OFFSET=0x80000000
1070 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1071 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1075 int "Maximum number of CPUs (2-32)"
1076 range 2 16 if DEBUG_KMAP_LOCAL
1077 range 2 32 if !DEBUG_KMAP_LOCAL
1081 The maximum number of CPUs that the kernel can support.
1082 Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1083 debugging is enabled, which uses half of the per-CPU fixmap
1084 slots as guard regions.
1087 bool "Support for hot-pluggable CPUs"
1089 select GENERIC_IRQ_MIGRATION
1091 Say Y here to experiment with turning CPUs off and on. CPUs
1092 can be controlled through /sys/devices/system/cpu.
1095 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1096 depends on HAVE_ARM_SMCCC
1099 Say Y here if you want Linux to communicate with system firmware
1100 implementing the PSCI specification for CPU-centric power
1101 management operations described in ARM document number ARM DEN
1102 0022A ("Power State Coordination Interface System Software on
1107 default 128 if SOC_AT91RM9200
1111 depends on HZ_FIXED = 0
1112 prompt "Timer frequency"
1136 default HZ_FIXED if HZ_FIXED != 0
1137 default 100 if HZ_100
1138 default 200 if HZ_200
1139 default 250 if HZ_250
1140 default 300 if HZ_300
1141 default 500 if HZ_500
1145 def_bool HIGH_RES_TIMERS
1147 config THUMB2_KERNEL
1148 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1149 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1150 default y if CPU_THUMBONLY
1153 By enabling this option, the kernel will be compiled in
1158 config ARM_PATCH_IDIV
1159 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1163 The ARM compiler inserts calls to __aeabi_idiv() and
1164 __aeabi_uidiv() when it needs to perform division on signed
1165 and unsigned integers. Some v7 CPUs have support for the sdiv
1166 and udiv instructions that can be used to implement those
1169 Enabling this option allows the kernel to modify itself to
1170 replace the first two instructions of these library functions
1171 with the sdiv or udiv plus "bx lr" instructions when the CPU
1172 it is running on supports them. Typically this will be faster
1173 and less power intensive than running the original library
1174 code to do integer division.
1177 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1178 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1179 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1181 This option allows for the kernel to be compiled using the latest
1182 ARM ABI (aka EABI). This is only useful if you are using a user
1183 space environment that is also compiled with EABI.
1185 Since there are major incompatibilities between the legacy ABI and
1186 EABI, especially with regard to structure member alignment, this
1187 option also changes the kernel syscall calling convention to
1188 disambiguate both ABIs and allow for backward compatibility support
1189 (selected with CONFIG_OABI_COMPAT).
1191 To use this you need GCC version 4.0.0 or later.
1194 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1195 depends on AEABI && !THUMB2_KERNEL
1197 This option preserves the old syscall interface along with the
1198 new (ARM EABI) one. It also provides a compatibility layer to
1199 intercept syscalls that have structure arguments which layout
1200 in memory differs between the legacy ABI and the new ARM EABI
1201 (only for non "thumb" binaries). This option adds a tiny
1202 overhead to all syscalls and produces a slightly larger kernel.
1204 The seccomp filter system will not be available when this is
1205 selected, since there is no way yet to sensibly distinguish
1206 between calling conventions during filtering.
1208 If you know you'll be using only pure EABI user space then you
1209 can say N here. If this option is not selected and you attempt
1210 to execute a legacy ABI binary then the result will be
1211 UNPREDICTABLE (in fact it can be predicted that it won't work
1212 at all). If in doubt say N.
1214 config ARCH_SELECT_MEMORY_MODEL
1217 config ARCH_FLATMEM_ENABLE
1218 def_bool !(ARCH_RPC || ARCH_SA1100)
1220 config ARCH_SPARSEMEM_ENABLE
1221 def_bool !ARCH_FOOTBRIDGE
1222 select SPARSEMEM_STATIC if SPARSEMEM
1225 bool "High Memory Support"
1228 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY
1230 The address space of ARM processors is only 4 Gigabytes large
1231 and it has to accommodate user address space, kernel address
1232 space as well as some memory mapped IO. That means that, if you
1233 have a large amount of physical memory and/or IO, not all of the
1234 memory can be "permanently mapped" by the kernel. The physical
1235 memory that is not permanently mapped is called "high memory".
1237 Depending on the selected kernel/user memory split, minimum
1238 vmalloc space and actual amount of RAM, you may not need this
1239 option which should result in a slightly faster kernel.
1244 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1248 The VM uses one page of physical memory for each page table.
1249 For systems with a lot of processes, this can use a lot of
1250 precious low memory, eventually leading to low memory being
1251 consumed by page tables. Setting this option will allow
1252 user-space 2nd level page tables to reside in high memory.
1254 config CPU_SW_DOMAIN_PAN
1255 bool "Enable use of CPU domains to implement privileged no-access"
1256 depends on MMU && !ARM_LPAE
1259 Increase kernel security by ensuring that normal kernel accesses
1260 are unable to access userspace addresses. This can help prevent
1261 use-after-free bugs becoming an exploitable privilege escalation
1262 by ensuring that magic values (such as LIST_POISON) will always
1263 fault when dereferenced.
1265 CPUs with low-vector mappings use a best-efforts implementation.
1266 Their lower 1MB needs to remain accessible for the vectors, but
1267 the remainder of userspace will become appropriately inaccessible.
1269 config HW_PERF_EVENTS
1273 config ARM_MODULE_PLTS
1274 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1276 select KASAN_VMALLOC if KASAN
1279 Allocate PLTs when loading modules so that jumps and calls whose
1280 targets are too far away for their relative offsets to be encoded
1281 in the instructions themselves can be bounced via veneers in the
1282 module's PLT. This allows modules to be allocated in the generic
1283 vmalloc area after the dedicated module memory area has been
1284 exhausted. The modules will use slightly more memory, but after
1285 rounding up to page size, the actual memory footprint is usually
1288 Disabling this is usually safe for small single-platform
1289 configurations. If unsure, say y.
1291 config ARCH_FORCE_MAX_ORDER
1292 int "Order of maximal physically contiguous allocations"
1293 default "11" if SOC_AM33XX
1294 default "8" if SA1111
1297 The kernel page allocator limits the size of maximal physically
1298 contiguous allocations. The limit is called MAX_ORDER and it
1299 defines the maximal power of two of number of pages that can be
1300 allocated as a single contiguous block. This option allows
1301 overriding the default setting when ability to allocate very
1302 large blocks of physically contiguous memory is required.
1304 Don't change if unsure.
1306 config ALIGNMENT_TRAP
1307 def_bool CPU_CP15_MMU
1308 select HAVE_PROC_CPU if PROC_FS
1310 ARM processors cannot fetch/store information which is not
1311 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1312 address divisible by 4. On 32-bit ARM processors, these non-aligned
1313 fetch/store instructions will be emulated in software if you say
1314 here, which has a severe performance impact. This is necessary for
1315 correct operation of some network protocols. With an IP-only
1316 configuration it is safe to say N, otherwise say Y.
1318 config UACCESS_WITH_MEMCPY
1319 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1321 default y if CPU_FEROCEON
1323 Implement faster copy_to_user and clear_user methods for CPU
1324 cores where a 8-word STM instruction give significantly higher
1325 memory write throughput than a sequence of individual 32bit stores.
1327 A possible side effect is a slight increase in scheduling latency
1328 between threads sharing the same address space if they invoke
1329 such copy operations with large buffers.
1331 However, if the CPU data cache is using a write-allocate mode,
1332 this option is unlikely to provide any performance gain.
1335 bool "Enable paravirtualization code"
1337 This changes the kernel so it can modify itself when it is run
1338 under a hypervisor, potentially improving performance significantly
1339 over full virtualization.
1341 config PARAVIRT_TIME_ACCOUNTING
1342 bool "Paravirtual steal time accounting"
1345 Select this option to enable fine granularity task steal time
1346 accounting. Time spent executing other tasks in parallel with
1347 the current vCPU is discounted from the vCPU power. To account for
1348 that, there can be a small performance impact.
1350 If in doubt, say N here.
1357 bool "Xen guest support on ARM"
1358 depends on ARM && AEABI && OF
1359 depends on CPU_V7 && !CPU_V6
1360 depends on !GENERIC_ATOMIC64
1362 select ARCH_DMA_ADDR_T_64BIT
1368 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1370 config CC_HAVE_STACKPROTECTOR_TLS
1371 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1373 config STACKPROTECTOR_PER_TASK
1374 bool "Use a unique stack canary value for each task"
1375 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA
1376 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS
1377 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS
1380 Due to the fact that GCC uses an ordinary symbol reference from
1381 which to load the value of the stack canary, this value can only
1382 change at reboot time on SMP systems, and all tasks running in the
1383 kernel's address space are forced to use the same canary value for
1384 the entire duration that the system is up.
1386 Enable this option to switch to a different method that uses a
1387 different canary value for each task.
1394 bool "Flattened Device Tree support"
1398 Include support for flattened device tree machine descriptions.
1400 config ARCH_WANT_FLAT_DTB_INSTALL
1404 bool "Support for the traditional ATAGS boot data passing"
1407 This is the traditional way of passing data to the kernel at boot
1408 time. If you are solely relying on the flattened device tree (or
1409 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1410 to remove ATAGS support from your kernel binary.
1412 config DEPRECATED_PARAM_STRUCT
1413 bool "Provide old way to pass kernel parameters"
1416 This was deprecated in 2001 and announced to live on for 5 years.
1417 Some old boot loaders still use this way.
1419 # Compressed boot loader in ROM. Yes, we really want to ask about
1420 # TEXT and BSS so we preserve their values in the config files.
1421 config ZBOOT_ROM_TEXT
1422 hex "Compressed ROM boot loader base address"
1425 The physical address at which the ROM-able zImage is to be
1426 placed in the target. Platforms which normally make use of
1427 ROM-able zImage formats normally set this to a suitable
1428 value in their defconfig file.
1430 If ZBOOT_ROM is not enabled, this has no effect.
1432 config ZBOOT_ROM_BSS
1433 hex "Compressed ROM boot loader BSS address"
1436 The base address of an area of read/write memory in the target
1437 for the ROM-able zImage which must be available while the
1438 decompressor is running. It must be large enough to hold the
1439 entire decompressed kernel plus an additional 128 KiB.
1440 Platforms which normally make use of ROM-able zImage formats
1441 normally set this to a suitable value in their defconfig file.
1443 If ZBOOT_ROM is not enabled, this has no effect.
1446 bool "Compressed boot loader in ROM/flash"
1447 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1448 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1450 Say Y here if you intend to execute your compressed kernel image
1451 (zImage) directly from ROM or flash. If unsure, say N.
1453 config ARM_APPENDED_DTB
1454 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1457 With this option, the boot code will look for a device tree binary
1458 (DTB) appended to zImage
1459 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1461 This is meant as a backward compatibility convenience for those
1462 systems with a bootloader that can't be upgraded to accommodate
1463 the documented boot protocol using a device tree.
1465 Beware that there is very little in terms of protection against
1466 this option being confused by leftover garbage in memory that might
1467 look like a DTB header after a reboot if no actual DTB is appended
1468 to zImage. Do not leave this option active in a production kernel
1469 if you don't intend to always append a DTB. Proper passing of the
1470 location into r2 of a bootloader provided DTB is always preferable
1473 config ARM_ATAG_DTB_COMPAT
1474 bool "Supplement the appended DTB with traditional ATAG information"
1475 depends on ARM_APPENDED_DTB
1477 Some old bootloaders can't be updated to a DTB capable one, yet
1478 they provide ATAGs with memory configuration, the ramdisk address,
1479 the kernel cmdline string, etc. Such information is dynamically
1480 provided by the bootloader and can't always be stored in a static
1481 DTB. To allow a device tree enabled kernel to be used with such
1482 bootloaders, this option allows zImage to extract the information
1483 from the ATAG list and store it at run time into the appended DTB.
1486 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1487 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1489 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1490 bool "Use bootloader kernel arguments if available"
1492 Uses the command-line options passed by the boot loader instead of
1493 the device tree bootargs property. If the boot loader doesn't provide
1494 any, the device tree bootargs property will be used.
1496 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1497 bool "Extend with bootloader kernel arguments"
1499 The command-line arguments provided by the boot loader will be
1500 appended to the the device tree bootargs property.
1505 string "Default kernel command string"
1508 On some architectures (e.g. CATS), there is currently no way
1509 for the boot loader to pass arguments to the kernel. For these
1510 architectures, you should supply some command-line options at build
1511 time by entering them here. As a minimum, you should specify the
1512 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1515 prompt "Kernel command line type" if CMDLINE != ""
1516 default CMDLINE_FROM_BOOTLOADER
1518 config CMDLINE_FROM_BOOTLOADER
1519 bool "Use bootloader kernel arguments if available"
1521 Uses the command-line options passed by the boot loader. If
1522 the boot loader doesn't provide any, the default kernel command
1523 string provided in CMDLINE will be used.
1525 config CMDLINE_EXTEND
1526 bool "Extend bootloader kernel arguments"
1528 The command-line arguments provided by the boot loader will be
1529 appended to the default kernel command string.
1531 config CMDLINE_FORCE
1532 bool "Always use the default kernel command string"
1534 Always use the default kernel command string, even if the boot
1535 loader passes other arguments to the kernel.
1536 This is useful if you cannot or don't want to change the
1537 command-line options your boot loader passes to the kernel.
1541 bool "Kernel Execute-In-Place from ROM"
1542 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1543 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP
1545 Execute-In-Place allows the kernel to run from non-volatile storage
1546 directly addressable by the CPU, such as NOR flash. This saves RAM
1547 space since the text section of the kernel is not loaded from flash
1548 to RAM. Read-write sections, such as the data section and stack,
1549 are still copied to RAM. The XIP kernel is not compressed since
1550 it has to run directly from flash, so it will take more space to
1551 store it. The flash address used to link the kernel object files,
1552 and for storing it, is configuration dependent. Therefore, if you
1553 say Y here, you must know the proper physical address where to
1554 store the kernel image depending on your own flash memory usage.
1556 Also note that the make target becomes "make xipImage" rather than
1557 "make zImage" or "make Image". The final kernel binary to put in
1558 ROM memory will be arch/arm/boot/xipImage.
1562 config XIP_PHYS_ADDR
1563 hex "XIP Kernel Physical Location"
1564 depends on XIP_KERNEL
1565 default "0x00080000"
1567 This is the physical address in your flash memory the kernel will
1568 be linked for and stored to. This address is dependent on your
1571 config XIP_DEFLATED_DATA
1572 bool "Store kernel .data section compressed in ROM"
1573 depends on XIP_KERNEL
1576 Before the kernel is actually executed, its .data section has to be
1577 copied to RAM from ROM. This option allows for storing that data
1578 in compressed form and decompressed to RAM rather than merely being
1579 copied, saving some precious ROM space. A possible drawback is a
1580 slightly longer boot delay.
1582 config ARCH_SUPPORTS_KEXEC
1583 def_bool (!SMP || PM_SLEEP_SMP) && MMU
1586 bool "Export atags in procfs"
1587 depends on ATAGS && KEXEC
1590 Should the atags used to boot the kernel be exported in an "atags"
1591 file in procfs. Useful with kexec.
1593 config ARCH_SUPPORTS_CRASH_DUMP
1596 config AUTO_ZRELADDR
1597 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM
1598 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
1600 ZRELADDR is the physical address where the decompressed kernel
1601 image will be placed. If AUTO_ZRELADDR is selected, the address
1602 will be determined at run-time, either by masking the current IP
1603 with 0xf8000000, or, if invalid, from the DTB passed in r2.
1604 This assumes the zImage being placed in the first 128MB from
1611 bool "UEFI runtime support"
1612 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1614 select EFI_PARAMS_FROM_FDT
1616 select EFI_GENERIC_STUB
1617 select EFI_RUNTIME_WRAPPERS
1619 This option provides support for runtime services provided
1620 by UEFI firmware (such as non-volatile variables, realtime
1621 clock, and platform reset). A UEFI stub is also provided to
1622 allow the kernel to be booted as an EFI application. This
1623 is only useful for kernels that may run on systems that have
1627 bool "Enable support for SMBIOS (DMI) tables"
1631 This enables SMBIOS/DMI feature for systems.
1633 This option is only useful on systems that have UEFI firmware.
1634 However, even with this option, the resultant kernel should
1635 continue to boot on existing non-UEFI platforms.
1637 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1638 i.e., the the practice of identifying the platform via DMI to
1639 decide whether certain workarounds for buggy hardware and/or
1640 firmware need to be enabled. This would require the DMI subsystem
1641 to be enabled much earlier than we do on ARM, which is non-trivial.
1645 menu "CPU Power Management"
1647 source "drivers/cpufreq/Kconfig"
1649 source "drivers/cpuidle/Kconfig"
1653 menu "Floating point emulation"
1655 comment "At least one emulation must be selected"
1658 bool "NWFPE math emulation"
1659 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1661 Say Y to include the NWFPE floating point emulator in the kernel.
1662 This is necessary to run most binaries. Linux does not currently
1663 support floating point hardware so you need to say Y here even if
1664 your machine has an FPA or floating point co-processor podule.
1666 You may say N here if you are going to load the Acorn FPEmulator
1667 early in the bootup.
1670 bool "Support extended precision"
1671 depends on FPE_NWFPE
1673 Say Y to include 80-bit support in the kernel floating-point
1674 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1675 Note that gcc does not generate 80-bit operations by default,
1676 so in most cases this option only enlarges the size of the
1677 floating point emulator without any good reason.
1679 You almost surely want to say N here.
1682 bool "FastFPE math emulation (EXPERIMENTAL)"
1683 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1685 Say Y here to include the FAST floating point emulator in the kernel.
1686 This is an experimental much faster emulator which now also has full
1687 precision for the mantissa. It does not support any exceptions.
1688 It is very simple, and approximately 3-6 times faster than NWFPE.
1690 It should be sufficient for most programs. It may be not suitable
1691 for scientific calculations, but you have to check this for yourself.
1692 If you do not feel you need a faster FP emulation you should better
1696 bool "VFP-format floating point maths"
1697 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1699 Say Y to include VFP support code in the kernel. This is needed
1700 if your hardware includes a VFP unit.
1702 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for
1703 release notes and additional status information.
1705 Say N if your target does not have VFP hardware.
1713 bool "Advanced SIMD (NEON) Extension support"
1714 depends on VFPv3 && CPU_V7
1716 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1719 config KERNEL_MODE_NEON
1720 bool "Support for NEON in kernel mode"
1721 depends on NEON && AEABI
1723 Say Y to include support for NEON in kernel mode.
1727 menu "Power management options"
1729 source "kernel/power/Kconfig"
1731 config ARCH_SUSPEND_POSSIBLE
1732 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1733 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
1736 config ARM_CPU_SUSPEND
1737 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
1738 depends on ARCH_SUSPEND_POSSIBLE
1740 config ARCH_HIBERNATION_POSSIBLE
1743 default y if ARCH_SUSPEND_POSSIBLE
1747 source "arch/arm/Kconfig.assembler"