1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_HAS_BINFMT_FLAT
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DEVMEM_IS_ALLOWED
9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
10 select ARCH_HAS_ELF_RANDOMIZE
11 select ARCH_HAS_FORTIFY_SOURCE
12 select ARCH_HAS_KEEPINITRD
14 select ARCH_HAS_MEMBARRIER_SYNC_CORE
15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
17 select ARCH_HAS_PHYS_TO_DMA
18 select ARCH_HAS_SETUP_DMA_OPS
19 select ARCH_HAS_SET_MEMORY
20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
21 select ARCH_HAS_STRICT_MODULE_RWX if MMU
22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB
23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
26 select ARCH_HAVE_CUSTOM_GPIO_H
27 select ARCH_HAS_GCOV_PROFILE_ALL
28 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC
29 select ARCH_MIGHT_HAVE_PC_PARPORT
30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
33 select ARCH_SUPPORTS_ATOMIC_RMW
34 select ARCH_USE_BUILTIN_BSWAP
35 select ARCH_USE_CMPXCHG_LOCKREF
36 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
37 select ARCH_WANT_IPC_PARSE_VERSION
38 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
39 select BUILDTIME_TABLE_SORT if MMU
40 select CLONE_BACKWARDS
41 select CPU_PM if SUSPEND || CPU_IDLE
42 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
43 select DMA_DECLARE_COHERENT
45 select DMA_REMAP if MMU
47 select EDAC_ATOMIC_SCRUB
48 select GENERIC_ALLOCATOR
49 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
50 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
51 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
52 select GENERIC_IRQ_IPI if SMP
53 select GENERIC_CPU_AUTOPROBE
54 select GENERIC_EARLY_IOREMAP
55 select GENERIC_IDLE_POLL_SETUP
56 select GENERIC_IRQ_PROBE
57 select GENERIC_IRQ_SHOW
58 select GENERIC_IRQ_SHOW_LEVEL
59 select GENERIC_PCI_IOMAP
60 select GENERIC_SCHED_CLOCK
61 select GENERIC_SMP_IDLE_THREAD
62 select GENERIC_STRNCPY_FROM_USER
63 select GENERIC_STRNLEN_USER
64 select HANDLE_DOMAIN_IRQ
65 select HARDIRQS_SW_RESEND
66 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
67 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
68 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
69 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
70 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
71 select HAVE_ARCH_MMAP_RND_BITS if MMU
72 select HAVE_ARCH_SECCOMP
73 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
74 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
75 select HAVE_ARCH_TRACEHOOK
76 select HAVE_ARM_SMCCC if CPU_V7
77 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
78 select HAVE_CONTEXT_TRACKING
79 select HAVE_C_RECORDMCOUNT
80 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
81 select HAVE_DMA_CONTIGUOUS if MMU
82 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
83 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
84 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
85 select HAVE_EXIT_THREAD
86 select HAVE_FAST_GUP if ARM_LPAE
87 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
88 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
89 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
90 select HAVE_GCC_PLUGINS
91 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
92 select HAVE_IDE if PCI || ISA || PCMCIA
93 select HAVE_IRQ_TIME_ACCOUNTING
94 select HAVE_KERNEL_GZIP
95 select HAVE_KERNEL_LZ4
96 select HAVE_KERNEL_LZMA
97 select HAVE_KERNEL_LZO
99 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
100 select HAVE_KRETPROBES if HAVE_KPROBES
101 select HAVE_MOD_ARCH_SPECIFIC
103 select HAVE_OPROFILE if HAVE_PERF_EVENTS
104 select HAVE_OPTPROBES if !THUMB2_KERNEL
105 select HAVE_PERF_EVENTS
106 select HAVE_PERF_REGS
107 select HAVE_PERF_USER_STACK_DUMP
108 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
109 select HAVE_REGS_AND_STACK_ACCESS_API
111 select HAVE_STACKPROTECTOR
112 select HAVE_SYSCALL_TRACEPOINTS
114 select HAVE_VIRT_CPU_ACCOUNTING_GEN
115 select IRQ_FORCED_THREADING
116 select MODULES_USE_ELF_REL
117 select NEED_DMA_MAP_STATE
118 select OF_EARLY_FLATTREE if OF
120 select OLD_SIGSUSPEND3
121 select PCI_SYSCALL if PCI
122 select PERF_USE_VMALLOC
125 select SYS_SUPPORTS_APM_EMULATION
126 # Above selects are sorted alphabetically; please add new ones
127 # according to that. Thanks.
129 The ARM series is a line of low-power-consumption RISC chip designs
130 licensed by ARM Ltd and targeted at embedded applications and
131 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
132 manufactured, but legacy ARM-based PC hardware remains popular in
133 Europe. There is an ARM Linux project with a web page at
134 <http://www.arm.linux.org.uk/>.
136 config ARM_HAS_SG_CHAIN
139 config ARM_DMA_USE_IOMMU
141 select ARM_HAS_SG_CHAIN
142 select NEED_SG_DMA_LENGTH
146 config ARM_DMA_IOMMU_ALIGNMENT
147 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
151 DMA mapping framework by default aligns all buffers to the smallest
152 PAGE_SIZE order which is greater than or equal to the requested buffer
153 size. This works well for buffers up to a few hundreds kilobytes, but
154 for larger buffers it just a waste of address space. Drivers which has
155 relatively small addressing window (like 64Mib) might run out of
156 virtual space with just a few allocations.
158 With this parameter you can specify the maximum PAGE_SIZE order for
159 DMA IOMMU buffers. Larger buffers will be aligned only to this
160 specified order. The order is expressed as a power of two multiplied
165 config SYS_SUPPORTS_APM_EMULATION
170 select GENERIC_ALLOCATOR
181 config STACKTRACE_SUPPORT
185 config LOCKDEP_SUPPORT
189 config TRACE_IRQFLAGS_SUPPORT
193 config ARCH_HAS_ILOG2_U32
196 config ARCH_HAS_ILOG2_U64
199 config ARCH_HAS_BANDGAP
202 config FIX_EARLYCON_MEM
205 config GENERIC_HWEIGHT
209 config GENERIC_CALIBRATE_DELAY
213 config ARCH_MAY_HAVE_PC_FDC
219 config ARCH_SUPPORTS_UPROBES
222 config ARCH_HAS_DMA_SET_COHERENT_MASK
225 config GENERIC_ISA_DMA
231 config NEED_RET_TO_USER
237 config ARM_PATCH_PHYS_VIRT
238 bool "Patch physical to virtual translations at runtime" if EMBEDDED
240 depends on !XIP_KERNEL && MMU
242 Patch phys-to-virt and virt-to-phys translation functions at
243 boot and module load time according to the position of the
244 kernel in system memory.
246 This can only be used with non-XIP MMU kernels where the base
247 of physical memory is at a 2 MiB boundary.
249 Only disable this option if you know that you do not require
250 this feature (eg, building a kernel for a single machine) and
251 you need to shrink the kernel to the minimal size.
253 config NEED_MACH_IO_H
256 Select this when mach/io.h is required to provide special
257 definitions for this platform. The need for mach/io.h should
258 be avoided when possible.
260 config NEED_MACH_MEMORY_H
263 Select this when mach/memory.h is required to provide special
264 definitions for this platform. The need for mach/memory.h should
265 be avoided when possible.
268 hex "Physical address of main memory" if MMU
269 depends on !ARM_PATCH_PHYS_VIRT
270 default DRAM_BASE if !MMU
271 default 0x00000000 if ARCH_EBSA110 || \
273 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
274 default 0x20000000 if ARCH_S5PV210
275 default 0xc0000000 if ARCH_SA1100
277 Please provide the physical address corresponding to the
278 location of main memory in your system.
284 config PGTABLE_LEVELS
286 default 3 if ARM_LPAE
292 bool "MMU-based Paged Memory Management Support"
295 Select if you want MMU-based virtualised addressing space
296 support by paged memory management. If unsure, say 'Y'.
298 config ARCH_MMAP_RND_BITS_MIN
301 config ARCH_MMAP_RND_BITS_MAX
302 default 14 if PAGE_OFFSET=0x40000000
303 default 15 if PAGE_OFFSET=0x80000000
307 # The "ARM system type" choice list is ordered alphabetically by option
308 # text. Please add new entries in the option alphabetic order.
311 prompt "ARM system type"
312 default ARM_SINGLE_ARMV7M if !MMU
313 default ARCH_MULTIPLATFORM if MMU
315 config ARCH_MULTIPLATFORM
316 bool "Allow multiple platforms to be selected"
318 select ARCH_FLATMEM_ENABLE
319 select ARCH_SPARSEMEM_ENABLE
320 select ARCH_SELECT_MEMORY_MODEL
321 select ARM_HAS_SG_CHAIN
322 select ARM_PATCH_PHYS_VIRT
326 select GENERIC_CLOCKEVENTS
327 select GENERIC_IRQ_MULTI_HANDLER
329 select PCI_DOMAINS_GENERIC if PCI
333 config ARM_SINGLE_ARMV7M
334 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
341 select GENERIC_CLOCKEVENTS
348 select ARCH_USES_GETTIMEOFFSET
351 select NEED_MACH_IO_H
352 select NEED_MACH_MEMORY_H
355 This is an evaluation board for the StrongARM processor available
356 from Digital. It has limited hardware on-board, including an
357 Ethernet interface, two PCMCIA sockets, two serial ports and a
362 select ARCH_SPARSEMEM_ENABLE
364 imply ARM_PATCH_PHYS_VIRT
370 select GENERIC_CLOCKEVENTS
372 select HAVE_LEGACY_CLK
374 This enables support for the Cirrus EP93xx series of CPUs.
376 config ARCH_FOOTBRIDGE
380 select GENERIC_CLOCKEVENTS
382 select NEED_MACH_IO_H if !MMU
383 select NEED_MACH_MEMORY_H
385 Support for systems based on the DC21285 companion chip
386 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
394 select NEED_RET_TO_USER
398 Support for Intel's 80219 and IOP32X (XScale) family of
404 select ARCH_HAS_DMA_SET_COHERENT_MASK
405 select ARCH_SUPPORTS_BIG_ENDIAN
407 select DMABOUNCE if PCI
408 select GENERIC_CLOCKEVENTS
409 select GENERIC_IRQ_MULTI_HANDLER
415 select NEED_MACH_IO_H
416 select USB_EHCI_BIG_ENDIAN_DESC
417 select USB_EHCI_BIG_ENDIAN_MMIO
419 Support for Intel's IXP4XX (XScale) family of processors.
424 select GENERIC_CLOCKEVENTS
425 select GENERIC_IRQ_MULTI_HANDLER
431 select PLAT_ORION_LEGACY
433 select PM_GENERIC_DOMAINS if PM
435 Support for the Marvell Dove SoC 88AP510
438 bool "PXA2xx/PXA3xx-based"
441 select ARM_CPU_SUSPEND if PM
447 select CPU_XSCALE if !CPU_XSC3
448 select GENERIC_CLOCKEVENTS
449 select GENERIC_IRQ_MULTI_HANDLER
457 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
463 select ARCH_MAY_HAVE_PC_FDC
464 select ARCH_SPARSEMEM_ENABLE
465 select ARM_HAS_SG_CHAIN
469 select HAVE_PATA_PLATFORM
471 select NEED_MACH_IO_H
472 select NEED_MACH_MEMORY_H
475 On the Acorn Risc-PC, Linux can support the internal IDE disk and
476 CD-ROM interface, serial and parallel port, and the floppy drive.
481 select ARCH_SPARSEMEM_ENABLE
484 select TIMER_OF if OF
488 select GENERIC_CLOCKEVENTS
489 select GENERIC_IRQ_MULTI_HANDLER
494 select NEED_MACH_MEMORY_H
497 Support for StrongARM 11x0 based boards.
500 bool "Samsung S3C24XX SoCs"
502 select CLKSRC_SAMSUNG_PWM
503 select GENERIC_CLOCKEVENTS
506 select GENERIC_IRQ_MULTI_HANDLER
507 select HAVE_S3C2410_I2C if I2C
508 select HAVE_S3C_RTC if RTC_CLASS
509 select NEED_MACH_IO_H
510 select S3C2410_WATCHDOG
515 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
516 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
517 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
518 Samsung SMDK2410 development board (and derivatives).
523 select ARCH_HAS_HOLES_MEMORYMODEL
527 select GENERIC_CLOCKEVENTS
528 select GENERIC_IRQ_CHIP
529 select GENERIC_IRQ_MULTI_HANDLER
532 select HAVE_LEGACY_CLK
534 select NEED_MACH_IO_H if PCCARD
535 select NEED_MACH_MEMORY_H
538 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
542 menu "Multiple platform selection"
543 depends on ARCH_MULTIPLATFORM
545 comment "CPU Core family selection"
548 bool "ARMv4 based platforms (FA526)"
549 depends on !ARCH_MULTI_V6_V7
550 select ARCH_MULTI_V4_V5
553 config ARCH_MULTI_V4T
554 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
555 depends on !ARCH_MULTI_V6_V7
556 select ARCH_MULTI_V4_V5
557 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
558 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
559 CPU_ARM925T || CPU_ARM940T)
562 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
563 depends on !ARCH_MULTI_V6_V7
564 select ARCH_MULTI_V4_V5
565 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
566 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
567 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
569 config ARCH_MULTI_V4_V5
573 bool "ARMv6 based platforms (ARM11)"
574 select ARCH_MULTI_V6_V7
578 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
580 select ARCH_MULTI_V6_V7
584 config ARCH_MULTI_V6_V7
586 select MIGHT_HAVE_CACHE_L2X0
588 config ARCH_MULTI_CPU_AUTO
589 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
595 bool "Dummy Virtual Machine"
596 depends on ARCH_MULTI_V7
599 select ARM_GIC_V2M if PCI
601 select ARM_GIC_V3_ITS if PCI
603 select HAVE_ARM_ARCH_TIMER
604 select ARCH_SUPPORTS_BIG_ENDIAN
607 # This is sorted alphabetically by mach-* pathname. However, plat-*
608 # Kconfigs may be included either alphabetically (according to the
609 # plat- suffix) or along side the corresponding mach-* source.
611 source "arch/arm/mach-actions/Kconfig"
613 source "arch/arm/mach-alpine/Kconfig"
615 source "arch/arm/mach-artpec/Kconfig"
617 source "arch/arm/mach-asm9260/Kconfig"
619 source "arch/arm/mach-aspeed/Kconfig"
621 source "arch/arm/mach-at91/Kconfig"
623 source "arch/arm/mach-axxia/Kconfig"
625 source "arch/arm/mach-bcm/Kconfig"
627 source "arch/arm/mach-berlin/Kconfig"
629 source "arch/arm/mach-clps711x/Kconfig"
631 source "arch/arm/mach-cns3xxx/Kconfig"
633 source "arch/arm/mach-davinci/Kconfig"
635 source "arch/arm/mach-digicolor/Kconfig"
637 source "arch/arm/mach-dove/Kconfig"
639 source "arch/arm/mach-ep93xx/Kconfig"
641 source "arch/arm/mach-exynos/Kconfig"
643 source "arch/arm/mach-footbridge/Kconfig"
645 source "arch/arm/mach-gemini/Kconfig"
647 source "arch/arm/mach-highbank/Kconfig"
649 source "arch/arm/mach-hisi/Kconfig"
651 source "arch/arm/mach-imx/Kconfig"
653 source "arch/arm/mach-integrator/Kconfig"
655 source "arch/arm/mach-iop32x/Kconfig"
657 source "arch/arm/mach-ixp4xx/Kconfig"
659 source "arch/arm/mach-keystone/Kconfig"
661 source "arch/arm/mach-lpc32xx/Kconfig"
663 source "arch/arm/mach-mediatek/Kconfig"
665 source "arch/arm/mach-meson/Kconfig"
667 source "arch/arm/mach-milbeaut/Kconfig"
669 source "arch/arm/mach-mmp/Kconfig"
671 source "arch/arm/mach-moxart/Kconfig"
673 source "arch/arm/mach-mstar/Kconfig"
675 source "arch/arm/mach-mv78xx0/Kconfig"
677 source "arch/arm/mach-mvebu/Kconfig"
679 source "arch/arm/mach-mxs/Kconfig"
681 source "arch/arm/mach-nomadik/Kconfig"
683 source "arch/arm/mach-npcm/Kconfig"
685 source "arch/arm/mach-nspire/Kconfig"
687 source "arch/arm/plat-omap/Kconfig"
689 source "arch/arm/mach-omap1/Kconfig"
691 source "arch/arm/mach-omap2/Kconfig"
693 source "arch/arm/mach-orion5x/Kconfig"
695 source "arch/arm/mach-oxnas/Kconfig"
697 source "arch/arm/mach-picoxcell/Kconfig"
699 source "arch/arm/mach-prima2/Kconfig"
701 source "arch/arm/mach-pxa/Kconfig"
702 source "arch/arm/plat-pxa/Kconfig"
704 source "arch/arm/mach-qcom/Kconfig"
706 source "arch/arm/mach-rda/Kconfig"
708 source "arch/arm/mach-realtek/Kconfig"
710 source "arch/arm/mach-realview/Kconfig"
712 source "arch/arm/mach-rockchip/Kconfig"
714 source "arch/arm/mach-s3c/Kconfig"
716 source "arch/arm/mach-s5pv210/Kconfig"
718 source "arch/arm/mach-sa1100/Kconfig"
720 source "arch/arm/mach-shmobile/Kconfig"
722 source "arch/arm/mach-socfpga/Kconfig"
724 source "arch/arm/mach-spear/Kconfig"
726 source "arch/arm/mach-sti/Kconfig"
728 source "arch/arm/mach-stm32/Kconfig"
730 source "arch/arm/mach-sunxi/Kconfig"
732 source "arch/arm/mach-tango/Kconfig"
734 source "arch/arm/mach-tegra/Kconfig"
736 source "arch/arm/mach-u300/Kconfig"
738 source "arch/arm/mach-uniphier/Kconfig"
740 source "arch/arm/mach-ux500/Kconfig"
742 source "arch/arm/mach-versatile/Kconfig"
744 source "arch/arm/mach-vexpress/Kconfig"
746 source "arch/arm/mach-vt8500/Kconfig"
748 source "arch/arm/mach-zx/Kconfig"
750 source "arch/arm/mach-zynq/Kconfig"
752 # ARMv7-M architecture
754 bool "Energy Micro efm32"
755 depends on ARM_SINGLE_ARMV7M
758 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
762 bool "NXP LPC18xx/LPC43xx"
763 depends on ARM_SINGLE_ARMV7M
764 select ARCH_HAS_RESET_CONTROLLER
766 select CLKSRC_LPC32XX
769 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
770 high performance microcontrollers.
773 bool "ARM MPS2 platform"
774 depends on ARM_SINGLE_ARMV7M
778 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
779 with a range of available cores like Cortex-M3/M4/M7.
781 Please, note that depends which Application Note is used memory map
782 for the platform may vary, so adjustment of RAM base might be needed.
784 # Definitions to make life easier
790 select GENERIC_CLOCKEVENTS
796 select GENERIC_IRQ_CHIP
799 config PLAT_ORION_LEGACY
806 config PLAT_VERSATILE
809 source "arch/arm/mm/Kconfig"
812 bool "Enable iWMMXt support"
813 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
814 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
816 Enable support for iWMMXt context switching at run time if
817 running on a CPU that supports it.
820 source "arch/arm/Kconfig-nommu"
823 config PJ4B_ERRATA_4742
824 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
825 depends on CPU_PJ4B && MACH_ARMADA_370
828 When coming out of either a Wait for Interrupt (WFI) or a Wait for
829 Event (WFE) IDLE states, a specific timing sensitivity exists between
830 the retiring WFI/WFE instructions and the newly issued subsequent
831 instructions. This sensitivity can result in a CPU hang scenario.
833 The software must insert either a Data Synchronization Barrier (DSB)
834 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
837 config ARM_ERRATA_326103
838 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
841 Executing a SWP instruction to read-only memory does not set bit 11
842 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
843 treat the access as a read, preventing a COW from occurring and
844 causing the faulting task to livelock.
846 config ARM_ERRATA_411920
847 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
848 depends on CPU_V6 || CPU_V6K
850 Invalidation of the Instruction Cache operation can
851 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
852 It does not affect the MPCore. This option enables the ARM Ltd.
853 recommended workaround.
855 config ARM_ERRATA_430973
856 bool "ARM errata: Stale prediction on replaced interworking branch"
859 This option enables the workaround for the 430973 Cortex-A8
860 r1p* erratum. If a code sequence containing an ARM/Thumb
861 interworking branch is replaced with another code sequence at the
862 same virtual address, whether due to self-modifying code or virtual
863 to physical address re-mapping, Cortex-A8 does not recover from the
864 stale interworking branch prediction. This results in Cortex-A8
865 executing the new code sequence in the incorrect ARM or Thumb state.
866 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
867 and also flushes the branch target cache at every context switch.
868 Note that setting specific bits in the ACTLR register may not be
869 available in non-secure mode.
871 config ARM_ERRATA_458693
872 bool "ARM errata: Processor deadlock when a false hazard is created"
874 depends on !ARCH_MULTIPLATFORM
876 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
877 erratum. For very specific sequences of memory operations, it is
878 possible for a hazard condition intended for a cache line to instead
879 be incorrectly associated with a different cache line. This false
880 hazard might then cause a processor deadlock. The workaround enables
881 the L1 caching of the NEON accesses and disables the PLD instruction
882 in the ACTLR register. Note that setting specific bits in the ACTLR
883 register may not be available in non-secure mode.
885 config ARM_ERRATA_460075
886 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
888 depends on !ARCH_MULTIPLATFORM
890 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
891 erratum. Any asynchronous access to the L2 cache may encounter a
892 situation in which recent store transactions to the L2 cache are lost
893 and overwritten with stale memory contents from external memory. The
894 workaround disables the write-allocate mode for the L2 cache via the
895 ACTLR register. Note that setting specific bits in the ACTLR register
896 may not be available in non-secure mode.
898 config ARM_ERRATA_742230
899 bool "ARM errata: DMB operation may be faulty"
900 depends on CPU_V7 && SMP
901 depends on !ARCH_MULTIPLATFORM
903 This option enables the workaround for the 742230 Cortex-A9
904 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
905 between two write operations may not ensure the correct visibility
906 ordering of the two writes. This workaround sets a specific bit in
907 the diagnostic register of the Cortex-A9 which causes the DMB
908 instruction to behave as a DSB, ensuring the correct behaviour of
911 config ARM_ERRATA_742231
912 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
913 depends on CPU_V7 && SMP
914 depends on !ARCH_MULTIPLATFORM
916 This option enables the workaround for the 742231 Cortex-A9
917 (r2p0..r2p2) erratum. Under certain conditions, specific to the
918 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
919 accessing some data located in the same cache line, may get corrupted
920 data due to bad handling of the address hazard when the line gets
921 replaced from one of the CPUs at the same time as another CPU is
922 accessing it. This workaround sets specific bits in the diagnostic
923 register of the Cortex-A9 which reduces the linefill issuing
924 capabilities of the processor.
926 config ARM_ERRATA_643719
927 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
928 depends on CPU_V7 && SMP
931 This option enables the workaround for the 643719 Cortex-A9 (prior to
932 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
933 register returns zero when it should return one. The workaround
934 corrects this value, ensuring cache maintenance operations which use
935 it behave as intended and avoiding data corruption.
937 config ARM_ERRATA_720789
938 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
941 This option enables the workaround for the 720789 Cortex-A9 (prior to
942 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
943 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
944 As a consequence of this erratum, some TLB entries which should be
945 invalidated are not, resulting in an incoherency in the system page
946 tables. The workaround changes the TLB flushing routines to invalidate
947 entries regardless of the ASID.
949 config ARM_ERRATA_743622
950 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
952 depends on !ARCH_MULTIPLATFORM
954 This option enables the workaround for the 743622 Cortex-A9
955 (r2p*) erratum. Under very rare conditions, a faulty
956 optimisation in the Cortex-A9 Store Buffer may lead to data
957 corruption. This workaround sets a specific bit in the diagnostic
958 register of the Cortex-A9 which disables the Store Buffer
959 optimisation, preventing the defect from occurring. This has no
960 visible impact on the overall performance or power consumption of the
963 config ARM_ERRATA_751472
964 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
966 depends on !ARCH_MULTIPLATFORM
968 This option enables the workaround for the 751472 Cortex-A9 (prior
969 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
970 completion of a following broadcasted operation if the second
971 operation is received by a CPU before the ICIALLUIS has completed,
972 potentially leading to corrupted entries in the cache or TLB.
974 config ARM_ERRATA_754322
975 bool "ARM errata: possible faulty MMU translations following an ASID switch"
978 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
979 r3p*) erratum. A speculative memory access may cause a page table walk
980 which starts prior to an ASID switch but completes afterwards. This
981 can populate the micro-TLB with a stale entry which may be hit with
982 the new ASID. This workaround places two dsb instructions in the mm
983 switching code so that no page table walks can cross the ASID switch.
985 config ARM_ERRATA_754327
986 bool "ARM errata: no automatic Store Buffer drain"
987 depends on CPU_V7 && SMP
989 This option enables the workaround for the 754327 Cortex-A9 (prior to
990 r2p0) erratum. The Store Buffer does not have any automatic draining
991 mechanism and therefore a livelock may occur if an external agent
992 continuously polls a memory location waiting to observe an update.
993 This workaround defines cpu_relax() as smp_mb(), preventing correctly
994 written polling loops from denying visibility of updates to memory.
996 config ARM_ERRATA_364296
997 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1000 This options enables the workaround for the 364296 ARM1136
1001 r0p2 erratum (possible cache data corruption with
1002 hit-under-miss enabled). It sets the undocumented bit 31 in
1003 the auxiliary control register and the FI bit in the control
1004 register, thus disabling hit-under-miss without putting the
1005 processor into full low interrupt latency mode. ARM11MPCore
1008 config ARM_ERRATA_764369
1009 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1010 depends on CPU_V7 && SMP
1012 This option enables the workaround for erratum 764369
1013 affecting Cortex-A9 MPCore with two or more processors (all
1014 current revisions). Under certain timing circumstances, a data
1015 cache line maintenance operation by MVA targeting an Inner
1016 Shareable memory region may fail to proceed up to either the
1017 Point of Coherency or to the Point of Unification of the
1018 system. This workaround adds a DSB instruction before the
1019 relevant cache maintenance functions and sets a specific bit
1020 in the diagnostic control register of the SCU.
1022 config ARM_ERRATA_775420
1023 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1026 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1027 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
1028 operation aborts with MMU exception, it might cause the processor
1029 to deadlock. This workaround puts DSB before executing ISB if
1030 an abort may occur on cache maintenance.
1032 config ARM_ERRATA_798181
1033 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1034 depends on CPU_V7 && SMP
1036 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1037 adequately shooting down all use of the old entries. This
1038 option enables the Linux kernel workaround for this erratum
1039 which sends an IPI to the CPUs that are running the same ASID
1040 as the one being invalidated.
1042 config ARM_ERRATA_773022
1043 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1046 This option enables the workaround for the 773022 Cortex-A15
1047 (up to r0p4) erratum. In certain rare sequences of code, the
1048 loop buffer may deliver incorrect instructions. This
1049 workaround disables the loop buffer to avoid the erratum.
1051 config ARM_ERRATA_818325_852422
1052 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1055 This option enables the workaround for:
1056 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1057 instruction might deadlock. Fixed in r0p1.
1058 - Cortex-A12 852422: Execution of a sequence of instructions might
1059 lead to either a data corruption or a CPU deadlock. Not fixed in
1060 any Cortex-A12 cores yet.
1061 This workaround for all both errata involves setting bit[12] of the
1062 Feature Register. This bit disables an optimisation applied to a
1063 sequence of 2 instructions that use opposing condition codes.
1065 config ARM_ERRATA_821420
1066 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1069 This option enables the workaround for the 821420 Cortex-A12
1070 (all revs) erratum. In very rare timing conditions, a sequence
1071 of VMOV to Core registers instructions, for which the second
1072 one is in the shadow of a branch or abort, can lead to a
1073 deadlock when the VMOV instructions are issued out-of-order.
1075 config ARM_ERRATA_825619
1076 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1079 This option enables the workaround for the 825619 Cortex-A12
1080 (all revs) erratum. Within rare timing constraints, executing a
1081 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1082 and Device/Strongly-Ordered loads and stores might cause deadlock
1084 config ARM_ERRATA_857271
1085 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1088 This option enables the workaround for the 857271 Cortex-A12
1089 (all revs) erratum. Under very rare timing conditions, the CPU might
1090 hang. The workaround is expected to have a < 1% performance impact.
1092 config ARM_ERRATA_852421
1093 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1096 This option enables the workaround for the 852421 Cortex-A17
1097 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1098 execution of a DMB ST instruction might fail to properly order
1099 stores from GroupA and stores from GroupB.
1101 config ARM_ERRATA_852423
1102 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1105 This option enables the workaround for:
1106 - Cortex-A17 852423: Execution of a sequence of instructions might
1107 lead to either a data corruption or a CPU deadlock. Not fixed in
1108 any Cortex-A17 cores yet.
1109 This is identical to Cortex-A12 erratum 852422. It is a separate
1110 config option from the A12 erratum due to the way errata are checked
1113 config ARM_ERRATA_857272
1114 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1117 This option enables the workaround for the 857272 Cortex-A17 erratum.
1118 This erratum is not known to be fixed in any A17 revision.
1119 This is identical to Cortex-A12 erratum 857271. It is a separate
1120 config option from the A12 erratum due to the way errata are checked
1125 source "arch/arm/common/Kconfig"
1132 Find out whether you have ISA slots on your motherboard. ISA is the
1133 name of a bus system, i.e. the way the CPU talks to the other stuff
1134 inside your box. Other bus systems are PCI, EISA, MicroChannel
1135 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1136 newer boards don't support it. If you have ISA, say Y, otherwise N.
1138 # Select ISA DMA controller support
1143 # Select ISA DMA interface
1147 config PCI_NANOENGINE
1148 bool "BSE nanoEngine PCI support"
1149 depends on SA1100_NANOENGINE
1151 Enable PCI on the BSE nanoEngine board.
1153 config ARM_ERRATA_814220
1154 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1157 The v7 ARM states that all cache and branch predictor maintenance
1158 operations that do not specify an address execute, relative to
1159 each other, in program order.
1160 However, because of this erratum, an L2 set/way cache maintenance
1161 operation can overtake an L1 set/way cache maintenance operation.
1162 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1167 menu "Kernel Features"
1172 This option should be selected by machines which have an SMP-
1175 The only effect of this option is to make the SMP-related
1176 options available to the user for configuration.
1179 bool "Symmetric Multi-Processing"
1180 depends on CPU_V6K || CPU_V7
1181 depends on GENERIC_CLOCKEVENTS
1183 depends on MMU || ARM_MPU
1186 This enables support for systems with more than one CPU. If you have
1187 a system with only one CPU, say N. If you have a system with more
1188 than one CPU, say Y.
1190 If you say N here, the kernel will run on uni- and multiprocessor
1191 machines, but will use only one CPU of a multiprocessor machine. If
1192 you say Y here, the kernel will run on many, but not all,
1193 uniprocessor machines. On a uniprocessor machine, the kernel
1194 will run faster if you say N here.
1196 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1197 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1198 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1200 If you don't know what to do here, say N.
1203 bool "Allow booting SMP kernel on uniprocessor systems"
1204 depends on SMP && !XIP_KERNEL && MMU
1207 SMP kernels contain instructions which fail on non-SMP processors.
1208 Enabling this option allows the kernel to modify itself to make
1209 these instructions safe. Disabling it allows about 1K of space
1212 If you don't know what to do here, say Y.
1214 config ARM_CPU_TOPOLOGY
1215 bool "Support cpu topology definition"
1216 depends on SMP && CPU_V7
1219 Support ARM cpu topology definition. The MPIDR register defines
1220 affinity between processors which is then used to describe the cpu
1221 topology of an ARM System.
1224 bool "Multi-core scheduler support"
1225 depends on ARM_CPU_TOPOLOGY
1227 Multi-core scheduler support improves the CPU scheduler's decision
1228 making when dealing with multi-core CPU chips at a cost of slightly
1229 increased overhead in some places. If unsure say N here.
1232 bool "SMT scheduler support"
1233 depends on ARM_CPU_TOPOLOGY
1235 Improves the CPU scheduler's decision making when dealing with
1236 MultiThreading at a cost of slightly increased overhead in some
1237 places. If unsure say N here.
1242 This option enables support for the ARM snoop control unit
1244 config HAVE_ARM_ARCH_TIMER
1245 bool "Architected timer support"
1247 select ARM_ARCH_TIMER
1249 This option enables support for the ARM architected timer
1254 This options enables support for the ARM timer and watchdog unit
1257 bool "Multi-Cluster Power Management"
1258 depends on CPU_V7 && SMP
1260 This option provides the common power management infrastructure
1261 for (multi-)cluster based systems, such as big.LITTLE based
1264 config MCPM_QUAD_CLUSTER
1268 To avoid wasting resources unnecessarily, MCPM only supports up
1269 to 2 clusters by default.
1270 Platforms with 3 or 4 clusters that use MCPM must select this
1271 option to allow the additional clusters to be managed.
1274 bool "big.LITTLE support (Experimental)"
1275 depends on CPU_V7 && SMP
1278 This option enables support selections for the big.LITTLE
1279 system architecture.
1282 bool "big.LITTLE switcher support"
1283 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1286 The big.LITTLE "switcher" provides the core functionality to
1287 transparently handle transition between a cluster of A15's
1288 and a cluster of A7's in a big.LITTLE system.
1290 config BL_SWITCHER_DUMMY_IF
1291 tristate "Simple big.LITTLE switcher user interface"
1292 depends on BL_SWITCHER && DEBUG_KERNEL
1294 This is a simple and dummy char dev interface to control
1295 the big.LITTLE switcher core code. It is meant for
1296 debugging purposes only.
1299 prompt "Memory split"
1303 Select the desired split between kernel and user memory.
1305 If you are not absolutely sure what you are doing, leave this
1309 bool "3G/1G user/kernel split"
1310 config VMSPLIT_3G_OPT
1311 depends on !ARM_LPAE
1312 bool "3G/1G user/kernel split (for full 1G low memory)"
1314 bool "2G/2G user/kernel split"
1316 bool "1G/3G user/kernel split"
1321 default PHYS_OFFSET if !MMU
1322 default 0x40000000 if VMSPLIT_1G
1323 default 0x80000000 if VMSPLIT_2G
1324 default 0xB0000000 if VMSPLIT_3G_OPT
1327 config KASAN_SHADOW_OFFSET
1330 default 0x1f000000 if PAGE_OFFSET=0x40000000
1331 default 0x5f000000 if PAGE_OFFSET=0x80000000
1332 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1333 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1337 int "Maximum number of CPUs (2-32)"
1343 bool "Support for hot-pluggable CPUs"
1345 select GENERIC_IRQ_MIGRATION
1347 Say Y here to experiment with turning CPUs off and on. CPUs
1348 can be controlled through /sys/devices/system/cpu.
1351 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1352 depends on HAVE_ARM_SMCCC
1355 Say Y here if you want Linux to communicate with system firmware
1356 implementing the PSCI specification for CPU-centric power
1357 management operations described in ARM document number ARM DEN
1358 0022A ("Power State Coordination Interface System Software on
1361 # The GPIO number here must be sorted by descending number. In case of
1362 # a multiplatform kernel, we just want the highest value required by the
1363 # selected platforms.
1366 default 2048 if ARCH_SOCFPGA
1367 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1368 ARCH_ZYNQ || ARCH_ASPEED
1369 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1370 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1371 default 416 if ARCH_SUNXI
1372 default 392 if ARCH_U8500
1373 default 352 if ARCH_VT8500
1374 default 288 if ARCH_ROCKCHIP
1375 default 264 if MACH_H4700
1378 Maximum number of GPIOs in the system.
1380 If unsure, leave the default value.
1384 default 200 if ARCH_EBSA110
1385 default 128 if SOC_AT91RM9200
1389 depends on HZ_FIXED = 0
1390 prompt "Timer frequency"
1414 default HZ_FIXED if HZ_FIXED != 0
1415 default 100 if HZ_100
1416 default 200 if HZ_200
1417 default 250 if HZ_250
1418 default 300 if HZ_300
1419 default 500 if HZ_500
1423 def_bool HIGH_RES_TIMERS
1425 config THUMB2_KERNEL
1426 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1427 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1428 default y if CPU_THUMBONLY
1431 By enabling this option, the kernel will be compiled in
1436 config ARM_PATCH_IDIV
1437 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1438 depends on CPU_32v7 && !XIP_KERNEL
1441 The ARM compiler inserts calls to __aeabi_idiv() and
1442 __aeabi_uidiv() when it needs to perform division on signed
1443 and unsigned integers. Some v7 CPUs have support for the sdiv
1444 and udiv instructions that can be used to implement those
1447 Enabling this option allows the kernel to modify itself to
1448 replace the first two instructions of these library functions
1449 with the sdiv or udiv plus "bx lr" instructions when the CPU
1450 it is running on supports them. Typically this will be faster
1451 and less power intensive than running the original library
1452 code to do integer division.
1455 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1456 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1457 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1459 This option allows for the kernel to be compiled using the latest
1460 ARM ABI (aka EABI). This is only useful if you are using a user
1461 space environment that is also compiled with EABI.
1463 Since there are major incompatibilities between the legacy ABI and
1464 EABI, especially with regard to structure member alignment, this
1465 option also changes the kernel syscall calling convention to
1466 disambiguate both ABIs and allow for backward compatibility support
1467 (selected with CONFIG_OABI_COMPAT).
1469 To use this you need GCC version 4.0.0 or later.
1472 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1473 depends on AEABI && !THUMB2_KERNEL
1475 This option preserves the old syscall interface along with the
1476 new (ARM EABI) one. It also provides a compatibility layer to
1477 intercept syscalls that have structure arguments which layout
1478 in memory differs between the legacy ABI and the new ARM EABI
1479 (only for non "thumb" binaries). This option adds a tiny
1480 overhead to all syscalls and produces a slightly larger kernel.
1482 The seccomp filter system will not be available when this is
1483 selected, since there is no way yet to sensibly distinguish
1484 between calling conventions during filtering.
1486 If you know you'll be using only pure EABI user space then you
1487 can say N here. If this option is not selected and you attempt
1488 to execute a legacy ABI binary then the result will be
1489 UNPREDICTABLE (in fact it can be predicted that it won't work
1490 at all). If in doubt say N.
1492 config ARCH_HAS_HOLES_MEMORYMODEL
1495 config ARCH_SELECT_MEMORY_MODEL
1498 config ARCH_FLATMEM_ENABLE
1501 config ARCH_SPARSEMEM_ENABLE
1503 select SPARSEMEM_STATIC if SPARSEMEM
1505 config HAVE_ARCH_PFN_VALID
1506 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1509 bool "High Memory Support"
1512 The address space of ARM processors is only 4 Gigabytes large
1513 and it has to accommodate user address space, kernel address
1514 space as well as some memory mapped IO. That means that, if you
1515 have a large amount of physical memory and/or IO, not all of the
1516 memory can be "permanently mapped" by the kernel. The physical
1517 memory that is not permanently mapped is called "high memory".
1519 Depending on the selected kernel/user memory split, minimum
1520 vmalloc space and actual amount of RAM, you may not need this
1521 option which should result in a slightly faster kernel.
1526 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1530 The VM uses one page of physical memory for each page table.
1531 For systems with a lot of processes, this can use a lot of
1532 precious low memory, eventually leading to low memory being
1533 consumed by page tables. Setting this option will allow
1534 user-space 2nd level page tables to reside in high memory.
1536 config CPU_SW_DOMAIN_PAN
1537 bool "Enable use of CPU domains to implement privileged no-access"
1538 depends on MMU && !ARM_LPAE
1541 Increase kernel security by ensuring that normal kernel accesses
1542 are unable to access userspace addresses. This can help prevent
1543 use-after-free bugs becoming an exploitable privilege escalation
1544 by ensuring that magic values (such as LIST_POISON) will always
1545 fault when dereferenced.
1547 CPUs with low-vector mappings use a best-efforts implementation.
1548 Their lower 1MB needs to remain accessible for the vectors, but
1549 the remainder of userspace will become appropriately inaccessible.
1551 config HW_PERF_EVENTS
1555 config SYS_SUPPORTS_HUGETLBFS
1559 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1563 config ARCH_WANT_GENERAL_HUGETLB
1566 config ARM_MODULE_PLTS
1567 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1571 Allocate PLTs when loading modules so that jumps and calls whose
1572 targets are too far away for their relative offsets to be encoded
1573 in the instructions themselves can be bounced via veneers in the
1574 module's PLT. This allows modules to be allocated in the generic
1575 vmalloc area after the dedicated module memory area has been
1576 exhausted. The modules will use slightly more memory, but after
1577 rounding up to page size, the actual memory footprint is usually
1580 Disabling this is usually safe for small single-platform
1581 configurations. If unsure, say y.
1583 config FORCE_MAX_ZONEORDER
1584 int "Maximum zone order"
1585 default "12" if SOC_AM33XX
1586 default "9" if SA1111 || ARCH_EFM32
1589 The kernel memory allocator divides physically contiguous memory
1590 blocks into "zones", where each zone is a power of two number of
1591 pages. This option selects the largest power of two that the kernel
1592 keeps in the memory allocator. If you need to allocate very large
1593 blocks of physically contiguous memory, then you may need to
1594 increase this value.
1596 This config option is actually maximum order plus one. For example,
1597 a value of 11 means that the largest free memory block is 2^10 pages.
1599 config ALIGNMENT_TRAP
1601 depends on CPU_CP15_MMU
1602 default y if !ARCH_EBSA110
1603 select HAVE_PROC_CPU if PROC_FS
1605 ARM processors cannot fetch/store information which is not
1606 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1607 address divisible by 4. On 32-bit ARM processors, these non-aligned
1608 fetch/store instructions will be emulated in software if you say
1609 here, which has a severe performance impact. This is necessary for
1610 correct operation of some network protocols. With an IP-only
1611 configuration it is safe to say N, otherwise say Y.
1613 config UACCESS_WITH_MEMCPY
1614 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1616 default y if CPU_FEROCEON
1618 Implement faster copy_to_user and clear_user methods for CPU
1619 cores where a 8-word STM instruction give significantly higher
1620 memory write throughput than a sequence of individual 32bit stores.
1622 A possible side effect is a slight increase in scheduling latency
1623 between threads sharing the same address space if they invoke
1624 such copy operations with large buffers.
1626 However, if the CPU data cache is using a write-allocate mode,
1627 this option is unlikely to provide any performance gain.
1630 bool "Enable paravirtualization code"
1632 This changes the kernel so it can modify itself when it is run
1633 under a hypervisor, potentially improving performance significantly
1634 over full virtualization.
1636 config PARAVIRT_TIME_ACCOUNTING
1637 bool "Paravirtual steal time accounting"
1640 Select this option to enable fine granularity task steal time
1641 accounting. Time spent executing other tasks in parallel with
1642 the current vCPU is discounted from the vCPU power. To account for
1643 that, there can be a small performance impact.
1645 If in doubt, say N here.
1652 bool "Xen guest support on ARM"
1653 depends on ARM && AEABI && OF
1654 depends on CPU_V7 && !CPU_V6
1655 depends on !GENERIC_ATOMIC64
1657 select ARCH_DMA_ADDR_T_64BIT
1663 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1665 config STACKPROTECTOR_PER_TASK
1666 bool "Use a unique stack canary value for each task"
1667 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1668 select GCC_PLUGIN_ARM_SSP_PER_TASK
1671 Due to the fact that GCC uses an ordinary symbol reference from
1672 which to load the value of the stack canary, this value can only
1673 change at reboot time on SMP systems, and all tasks running in the
1674 kernel's address space are forced to use the same canary value for
1675 the entire duration that the system is up.
1677 Enable this option to switch to a different method that uses a
1678 different canary value for each task.
1685 bool "Flattened Device Tree support"
1689 Include support for flattened device tree machine descriptions.
1692 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1695 This is the traditional way of passing data to the kernel at boot
1696 time. If you are solely relying on the flattened device tree (or
1697 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1698 to remove ATAGS support from your kernel binary. If unsure,
1701 config DEPRECATED_PARAM_STRUCT
1702 bool "Provide old way to pass kernel parameters"
1705 This was deprecated in 2001 and announced to live on for 5 years.
1706 Some old boot loaders still use this way.
1708 # Compressed boot loader in ROM. Yes, we really want to ask about
1709 # TEXT and BSS so we preserve their values in the config files.
1710 config ZBOOT_ROM_TEXT
1711 hex "Compressed ROM boot loader base address"
1714 The physical address at which the ROM-able zImage is to be
1715 placed in the target. Platforms which normally make use of
1716 ROM-able zImage formats normally set this to a suitable
1717 value in their defconfig file.
1719 If ZBOOT_ROM is not enabled, this has no effect.
1721 config ZBOOT_ROM_BSS
1722 hex "Compressed ROM boot loader BSS address"
1725 The base address of an area of read/write memory in the target
1726 for the ROM-able zImage which must be available while the
1727 decompressor is running. It must be large enough to hold the
1728 entire decompressed kernel plus an additional 128 KiB.
1729 Platforms which normally make use of ROM-able zImage formats
1730 normally set this to a suitable value in their defconfig file.
1732 If ZBOOT_ROM is not enabled, this has no effect.
1735 bool "Compressed boot loader in ROM/flash"
1736 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1737 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1739 Say Y here if you intend to execute your compressed kernel image
1740 (zImage) directly from ROM or flash. If unsure, say N.
1742 config ARM_APPENDED_DTB
1743 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1746 With this option, the boot code will look for a device tree binary
1747 (DTB) appended to zImage
1748 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1750 This is meant as a backward compatibility convenience for those
1751 systems with a bootloader that can't be upgraded to accommodate
1752 the documented boot protocol using a device tree.
1754 Beware that there is very little in terms of protection against
1755 this option being confused by leftover garbage in memory that might
1756 look like a DTB header after a reboot if no actual DTB is appended
1757 to zImage. Do not leave this option active in a production kernel
1758 if you don't intend to always append a DTB. Proper passing of the
1759 location into r2 of a bootloader provided DTB is always preferable
1762 config ARM_ATAG_DTB_COMPAT
1763 bool "Supplement the appended DTB with traditional ATAG information"
1764 depends on ARM_APPENDED_DTB
1766 Some old bootloaders can't be updated to a DTB capable one, yet
1767 they provide ATAGs with memory configuration, the ramdisk address,
1768 the kernel cmdline string, etc. Such information is dynamically
1769 provided by the bootloader and can't always be stored in a static
1770 DTB. To allow a device tree enabled kernel to be used with such
1771 bootloaders, this option allows zImage to extract the information
1772 from the ATAG list and store it at run time into the appended DTB.
1775 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1776 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1778 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1779 bool "Use bootloader kernel arguments if available"
1781 Uses the command-line options passed by the boot loader instead of
1782 the device tree bootargs property. If the boot loader doesn't provide
1783 any, the device tree bootargs property will be used.
1785 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1786 bool "Extend with bootloader kernel arguments"
1788 The command-line arguments provided by the boot loader will be
1789 appended to the the device tree bootargs property.
1794 string "Default kernel command string"
1797 On some architectures (EBSA110 and CATS), there is currently no way
1798 for the boot loader to pass arguments to the kernel. For these
1799 architectures, you should supply some command-line options at build
1800 time by entering them here. As a minimum, you should specify the
1801 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1804 prompt "Kernel command line type" if CMDLINE != ""
1805 default CMDLINE_FROM_BOOTLOADER
1808 config CMDLINE_FROM_BOOTLOADER
1809 bool "Use bootloader kernel arguments if available"
1811 Uses the command-line options passed by the boot loader. If
1812 the boot loader doesn't provide any, the default kernel command
1813 string provided in CMDLINE will be used.
1815 config CMDLINE_EXTEND
1816 bool "Extend bootloader kernel arguments"
1818 The command-line arguments provided by the boot loader will be
1819 appended to the default kernel command string.
1821 config CMDLINE_FORCE
1822 bool "Always use the default kernel command string"
1824 Always use the default kernel command string, even if the boot
1825 loader passes other arguments to the kernel.
1826 This is useful if you cannot or don't want to change the
1827 command-line options your boot loader passes to the kernel.
1831 bool "Kernel Execute-In-Place from ROM"
1832 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1834 Execute-In-Place allows the kernel to run from non-volatile storage
1835 directly addressable by the CPU, such as NOR flash. This saves RAM
1836 space since the text section of the kernel is not loaded from flash
1837 to RAM. Read-write sections, such as the data section and stack,
1838 are still copied to RAM. The XIP kernel is not compressed since
1839 it has to run directly from flash, so it will take more space to
1840 store it. The flash address used to link the kernel object files,
1841 and for storing it, is configuration dependent. Therefore, if you
1842 say Y here, you must know the proper physical address where to
1843 store the kernel image depending on your own flash memory usage.
1845 Also note that the make target becomes "make xipImage" rather than
1846 "make zImage" or "make Image". The final kernel binary to put in
1847 ROM memory will be arch/arm/boot/xipImage.
1851 config XIP_PHYS_ADDR
1852 hex "XIP Kernel Physical Location"
1853 depends on XIP_KERNEL
1854 default "0x00080000"
1856 This is the physical address in your flash memory the kernel will
1857 be linked for and stored to. This address is dependent on your
1860 config XIP_DEFLATED_DATA
1861 bool "Store kernel .data section compressed in ROM"
1862 depends on XIP_KERNEL
1865 Before the kernel is actually executed, its .data section has to be
1866 copied to RAM from ROM. This option allows for storing that data
1867 in compressed form and decompressed to RAM rather than merely being
1868 copied, saving some precious ROM space. A possible drawback is a
1869 slightly longer boot delay.
1872 bool "Kexec system call (EXPERIMENTAL)"
1873 depends on (!SMP || PM_SLEEP_SMP)
1877 kexec is a system call that implements the ability to shutdown your
1878 current kernel, and to start another kernel. It is like a reboot
1879 but it is independent of the system firmware. And like a reboot
1880 you can start any kernel with it, not just Linux.
1882 It is an ongoing process to be certain the hardware in a machine
1883 is properly shutdown, so do not be surprised if this code does not
1884 initially work for you.
1887 bool "Export atags in procfs"
1888 depends on ATAGS && KEXEC
1891 Should the atags used to boot the kernel be exported in an "atags"
1892 file in procfs. Useful with kexec.
1895 bool "Build kdump crash kernel (EXPERIMENTAL)"
1897 Generate crash dump after being started by kexec. This should
1898 be normally only set in special crash dump kernels which are
1899 loaded in the main kernel with kexec-tools into a specially
1900 reserved region and then later executed after a crash by
1901 kdump/kexec. The crash dump kernel must be compiled to a
1902 memory address not used by the main kernel
1904 For more details see Documentation/admin-guide/kdump/kdump.rst
1906 config AUTO_ZRELADDR
1907 bool "Auto calculation of the decompressed kernel image address"
1909 ZRELADDR is the physical address where the decompressed kernel
1910 image will be placed. If AUTO_ZRELADDR is selected, the address
1911 will be determined at run-time by masking the current IP with
1912 0xf8000000. This assumes the zImage being placed in the first 128MB
1913 from start of memory.
1919 bool "UEFI runtime support"
1920 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1922 select EFI_PARAMS_FROM_FDT
1924 select EFI_GENERIC_STUB
1925 select EFI_RUNTIME_WRAPPERS
1927 This option provides support for runtime services provided
1928 by UEFI firmware (such as non-volatile variables, realtime
1929 clock, and platform reset). A UEFI stub is also provided to
1930 allow the kernel to be booted as an EFI application. This
1931 is only useful for kernels that may run on systems that have
1935 bool "Enable support for SMBIOS (DMI) tables"
1939 This enables SMBIOS/DMI feature for systems.
1941 This option is only useful on systems that have UEFI firmware.
1942 However, even with this option, the resultant kernel should
1943 continue to boot on existing non-UEFI platforms.
1945 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1946 i.e., the the practice of identifying the platform via DMI to
1947 decide whether certain workarounds for buggy hardware and/or
1948 firmware need to be enabled. This would require the DMI subsystem
1949 to be enabled much earlier than we do on ARM, which is non-trivial.
1953 menu "CPU Power Management"
1955 source "drivers/cpufreq/Kconfig"
1957 source "drivers/cpuidle/Kconfig"
1961 menu "Floating point emulation"
1963 comment "At least one emulation must be selected"
1966 bool "NWFPE math emulation"
1967 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1969 Say Y to include the NWFPE floating point emulator in the kernel.
1970 This is necessary to run most binaries. Linux does not currently
1971 support floating point hardware so you need to say Y here even if
1972 your machine has an FPA or floating point co-processor podule.
1974 You may say N here if you are going to load the Acorn FPEmulator
1975 early in the bootup.
1978 bool "Support extended precision"
1979 depends on FPE_NWFPE
1981 Say Y to include 80-bit support in the kernel floating-point
1982 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1983 Note that gcc does not generate 80-bit operations by default,
1984 so in most cases this option only enlarges the size of the
1985 floating point emulator without any good reason.
1987 You almost surely want to say N here.
1990 bool "FastFPE math emulation (EXPERIMENTAL)"
1991 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1993 Say Y here to include the FAST floating point emulator in the kernel.
1994 This is an experimental much faster emulator which now also has full
1995 precision for the mantissa. It does not support any exceptions.
1996 It is very simple, and approximately 3-6 times faster than NWFPE.
1998 It should be sufficient for most programs. It may be not suitable
1999 for scientific calculations, but you have to check this for yourself.
2000 If you do not feel you need a faster FP emulation you should better
2004 bool "VFP-format floating point maths"
2005 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2007 Say Y to include VFP support code in the kernel. This is needed
2008 if your hardware includes a VFP unit.
2010 Please see <file:Documentation/arm/vfp/release-notes.rst> for
2011 release notes and additional status information.
2013 Say N if your target does not have VFP hardware.
2021 bool "Advanced SIMD (NEON) Extension support"
2022 depends on VFPv3 && CPU_V7
2024 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2027 config KERNEL_MODE_NEON
2028 bool "Support for NEON in kernel mode"
2029 depends on NEON && AEABI
2031 Say Y to include support for NEON in kernel mode.
2035 menu "Power management options"
2037 source "kernel/power/Kconfig"
2039 config ARCH_SUSPEND_POSSIBLE
2040 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2041 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2044 config ARM_CPU_SUSPEND
2045 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2046 depends on ARCH_SUSPEND_POSSIBLE
2048 config ARCH_HIBERNATION_POSSIBLE
2051 default y if ARCH_SUSPEND_POSSIBLE
2055 source "drivers/firmware/Kconfig"
2058 source "arch/arm/crypto/Kconfig"
2061 source "arch/arm/Kconfig.assembler"