1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright(c) 2015 EZchip Technologies.
6 #ifndef _PLAT_EZNPS_CTOP_H
7 #define _PLAT_EZNPS_CTOP_H
9 #ifndef CONFIG_ARC_PLAT_EZNPS
10 #error "Incorrect ctop.h include"
13 #include <linux/bits.h>
14 #include <linux/types.h>
15 #include <soc/nps/common.h>
17 /* core auxiliary registers */
19 #define CTOP_AUX_BASE (-0x800)
21 #define CTOP_AUX_BASE 0xFFFFF800
24 #define CTOP_AUX_GLOBAL_ID (CTOP_AUX_BASE + 0x000)
25 #define CTOP_AUX_CLUSTER_ID (CTOP_AUX_BASE + 0x004)
26 #define CTOP_AUX_CORE_ID (CTOP_AUX_BASE + 0x008)
27 #define CTOP_AUX_THREAD_ID (CTOP_AUX_BASE + 0x00C)
28 #define CTOP_AUX_LOGIC_GLOBAL_ID (CTOP_AUX_BASE + 0x010)
29 #define CTOP_AUX_LOGIC_CLUSTER_ID (CTOP_AUX_BASE + 0x014)
30 #define CTOP_AUX_LOGIC_CORE_ID (CTOP_AUX_BASE + 0x018)
31 #define CTOP_AUX_MT_CTRL (CTOP_AUX_BASE + 0x020)
32 #define CTOP_AUX_HW_COMPLY (CTOP_AUX_BASE + 0x024)
33 #define CTOP_AUX_DPC (CTOP_AUX_BASE + 0x02C)
34 #define CTOP_AUX_LPC (CTOP_AUX_BASE + 0x030)
35 #define CTOP_AUX_EFLAGS (CTOP_AUX_BASE + 0x080)
36 #define CTOP_AUX_GPA1 (CTOP_AUX_BASE + 0x08C)
37 #define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300)
39 /* EZchip core instructions */
40 #define CTOP_INST_HWSCHD_WFT_IE12 0x3E6F7344
41 #define CTOP_INST_HWSCHD_OFF_R4 0x3C6F00BF
42 #define CTOP_INST_HWSCHD_RESTORE_R4 0x3E6F7103
43 #define CTOP_INST_SCHD_RW 0x3E6F7004
44 #define CTOP_INST_SCHD_RD 0x3E6F7084
45 #define CTOP_INST_ASRI_0_R3 0x3B56003E
46 #define CTOP_INST_XEX_DI_R2_R2_R3 0x4A664C00
47 #define CTOP_INST_EXC_DI_R2_R2_R3 0x4A664C01
48 #define CTOP_INST_AADD_DI_R2_R2_R3 0x4A664C02
49 #define CTOP_INST_AAND_DI_R2_R2_R3 0x4A664C04
50 #define CTOP_INST_AOR_DI_R2_R2_R3 0x4A664C05
51 #define CTOP_INST_AXOR_DI_R2_R2_R3 0x4A664C06
53 /* Do not use D$ for address in 2G-3G */
54 #define HW_COMPLY_KRN_NOT_D_CACHED BIT(28)
56 #define NPS_MSU_EN_CFG 0x80
57 #define NPS_CRG_BLKID 0x480
58 #define NPS_CRG_SYNC_BIT BIT(0)
59 #define NPS_GIM_BLKID 0x5C0
61 /* GIM registers and fields*/
62 #define NPS_GIM_UART_LINE BIT(7)
63 #define NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE BIT(10)
64 #define NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE BIT(11)
65 #define NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE BIT(25)
66 #define NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE BIT(26)
69 /* Functional registers definition */
70 struct nps_host_reg_mtm_cfg {
73 u32 gen:1, gdis:1, clk_gate_dis:1, asb:1,
74 __reserved:9, nat:3, ten:16;
80 struct nps_host_reg_mtm_cpu_cfg {
83 u32 csa:22, dmsid:6, __reserved:3, cs:1;
89 struct nps_host_reg_thr_init {
92 u32 str:1, __reserved:27, thr_id:4;
98 struct nps_host_reg_thr_init_sts {
101 u32 bsy:1, err:1, __reserved:26, thr_id:4;
107 struct nps_host_reg_msu_en_cfg {
111 rtc_en:1, ipc_en:1, gim_1_en:1,
112 gim_0_en:1, ipi_en:1, buff_e_rls_bmuw:1,
113 buff_e_alc_bmuw:1, buff_i_rls_bmuw:1, buff_i_alc_bmuw:1,
114 buff_e_rls_bmue:1, buff_e_alc_bmue:1, buff_i_rls_bmue:1,
115 buff_i_alc_bmue:1, __reserved2:1, buff_e_pre_en:1,
116 buff_i_pre_en:1, pmuw_ja_en:1, pmue_ja_en:1,
117 pmuw_nj_en:1, pmue_nj_en:1, msu_en:1;
123 struct nps_host_reg_gim_p_int_dst {
126 u32 int_out_en:1, __reserved1:4,
127 is:1, intm:2, __reserved2:4,
128 nid:4, __reserved3:4, cid:4,
129 __reserved4:4, tid:4;
135 /* AUX registers definition */
136 struct nps_host_reg_aux_dpc {
139 u32 ien:1, men:1, hen:1, reserved:29;
145 struct nps_host_reg_aux_udmc {
148 u32 dcp:1, cme:1, __reserved:19, nat:3,
149 __reserved2:5, dcas:3;
155 struct nps_host_reg_aux_mt_ctrl {
158 u32 mten:1, hsen:1, scd:1, sten:1,
159 st_cnt:8, __reserved:8,
160 hs_cnt:8, __reserved1:4;
166 struct nps_host_reg_aux_hw_comply {
169 u32 me:1, le:1, te:1, knc:1, __reserved:28;
175 struct nps_host_reg_aux_lpc {
178 u32 mep:1, __reserved:31;
185 #define REG_GEN_PURP_0 nps_host_reg_non_cl(NPS_CRG_BLKID, 0x1BF)
188 #define REG_GIM_P_INT_EN_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x100)
189 #define REG_GIM_P_INT_POL_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x110)
190 #define REG_GIM_P_INT_SENS_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x114)
191 #define REG_GIM_P_INT_BLK_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x118)
192 #define REG_GIM_P_INT_DST_10 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x13A)
193 #define REG_GIM_P_INT_DST_11 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x13B)
194 #define REG_GIM_P_INT_DST_25 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x149)
195 #define REG_GIM_P_INT_DST_26 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x14A)
199 .macro GET_CPU_ID reg
200 lr \reg, [CTOP_AUX_LOGIC_GLOBAL_ID]
201 #ifndef CONFIG_EZNPS_MTM_EXT
206 #endif /* __ASSEMBLY__ */
208 #endif /* _PLAT_EZNPS_CTOP_H */