1 ===========================
2 drm/i915 Intel GFX Driver
3 ===========================
5 The drm/i915 driver supports all (with the exception of some very early
6 models) integrated GFX chipsets with both Intel display and rendering
7 blocks. This excludes a set of SoC platforms with an SGX rendering unit,
8 those have basic support through the gma500 drm driver.
10 Core Driver Infrastructure
11 ==========================
13 This section covers core driver infrastructure used by both the display
14 and the GEM parts of the driver.
16 Runtime Power Management
17 ------------------------
19 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
22 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
25 .. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c
31 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
32 :doc: interrupt handling
34 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
35 :functions: intel_irq_init intel_irq_init_hw intel_hpd_init
37 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
38 :functions: intel_runtime_pm_disable_interrupts
40 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
41 :functions: intel_runtime_pm_enable_interrupts
43 Intel GVT-g Guest Support(vGPU)
44 -------------------------------
46 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
47 :doc: Intel GVT-g guest support
49 .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
52 Intel GVT-g Host Support(vGPU device model)
53 -------------------------------------------
55 .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
56 :doc: Intel GVT-g host support
58 .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
64 .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_workarounds.c
65 :doc: Hardware workarounds
67 Display Hardware Handling
68 =========================
70 This section covers everything related to the display hardware including
71 the mode setting infrastructure, plane, sprite and cursor handling and
72 display, output probing and related topics.
74 Mode Setting Infrastructure
75 ---------------------------
77 The i915 driver is thus far the only DRM driver which doesn't use the
78 common DRM helper code to implement mode setting sequences. Thus it has
79 its own tailor-made infrastructure for executing a display configuration
85 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c
86 :doc: frontbuffer tracking
88 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h
91 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c
94 Display FIFO Underrun Reporting
95 -------------------------------
97 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c
98 :doc: fifo underrun handling
100 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c
106 This section covers plane configuration and composition with the primary
107 plane, sprites, cursors and overlays. This includes the infrastructure
108 to do atomic vsync'ed updates of all this state and also tightly coupled
109 topics like watermark setup and computation, framebuffer compression and
115 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c
116 :doc: atomic plane helpers
118 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c
121 Asynchronous Page Flip
122 ----------------------
124 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c
125 :doc: asynchronous flip implementation
130 This section covers output probing and related infrastructure like the
131 hotplug interrupt storm detection and mitigation code. Note that the
132 i915 driver still uses most of the common DRM helper code for output
133 probing, so those sections fully apply.
138 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c
141 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c
144 High Definition Audio
145 ---------------------
147 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c
148 :doc: High Definition Audio over HDMI and Display Port
150 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c
153 .. kernel-doc:: include/drm/i915_component.h
156 Intel HDMI LPE Audio Support
157 ----------------------------
159 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c
160 :doc: LPE Audio integration for HDMI or DP playback
162 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c
165 Panel Self Refresh PSR (PSR/SRD)
166 --------------------------------
168 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c
169 :doc: Panel Self Refresh (PSR/SRD)
171 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c
174 Frame Buffer Compression (FBC)
175 ------------------------------
177 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c
178 :doc: Frame Buffer Compression (FBC)
180 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c
183 Display Refresh Rate Switching (DRRS)
184 -------------------------------------
186 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
187 :doc: Display Refresh Rate Switching (DRRS)
189 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c
195 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c
201 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c
202 :doc: DMC Firmware Support
204 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c
207 Video BIOS Table (VBT)
208 ----------------------
210 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c
211 :doc: Video BIOS Table (VBT)
213 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c
216 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h
222 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c
225 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c
231 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c
234 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c
237 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h
243 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
246 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
252 Multicast/Replicated (MCR) Registers
253 ------------------------------------
255 .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
256 :doc: GT Multicast/Replicated (MCR) Register Support
258 .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c
261 Memory Management and Command Submission
262 ========================================
264 This sections covers all things related to the GEM implementation in the
270 An Intel GPU has multiple engines. There are several engine types:
272 - Render Command Streamer (RCS). An engine for rendering 3D and
274 - Blitting Command Streamer (BCS). An engine for performing blitting and/or
276 - Video Command Streamer. An engine used for video encoding and decoding. Also
277 sometimes called 'BSD' in hardware documentation.
278 - Video Enhancement Command Streamer (VECS). An engine for video enhancement.
279 Also sometimes called 'VEBOX' in hardware documentation.
280 - Compute Command Streamer (CCS). An engine that has access to the media and
281 GPGPU pipelines, but not the 3D pipeline.
282 - Graphics Security Controller (GSCCS). A dedicated engine for internal
283 communication with GSC controller on security related tasks like
284 High-bandwidth Digital Content Protection (HDCP), Protected Xe Path (PXP),
285 and HuC firmware authentication.
287 The Intel GPU family is a family of integrated GPU's using Unified
288 Memory Access. For having the GPU "do work", user space will feed the
289 GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`
290 or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will
291 instruct the GPU to perform work (for example rendering) and that work
292 needs memory from which to read and memory to which to write. All memory
293 is encapsulated within GEM buffer objects (usually created with the ioctl
294 `DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU
295 to create will also list all GEM buffer objects that the batchbuffer reads
296 and/or writes. For implementation details of memory management see
297 `GEM BO Management Implementation Details`_.
299 The i915 driver allows user space to create a context via the ioctl
300 `DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit
301 integer. Such a context should be viewed by user-space as -loosely-
302 analogous to the idea of a CPU process of an operating system. The i915
303 driver guarantees that commands issued to a fixed context are to be
304 executed so that writes of a previously issued command are seen by
305 reads of following commands. Actions issued between different contexts
306 (even if from the same file descriptor) are NOT given that guarantee
307 and the only way to synchronize across contexts (even from the same
308 file descriptor) is through the use of fences. At least as far back as
309 Gen4, also have that a context carries with it a GPU HW context;
310 the HW context is essentially (most of at least) the state of a GPU.
311 In addition to the ordering guarantees, the kernel will restore GPU
312 state via HW context when commands are issued to a context, this saves
313 user space the need to restore (most of at least) the GPU state at the
314 start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer
315 work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1)
316 to identify what context to use with the command.
318 The GPU has its own memory management and address space. The kernel
319 driver maintains the memory translation table for the GPU. For older
320 GPUs (i.e. those before Gen8), there is a single global such translation
321 table, a global Graphics Translation Table (GTT). For newer generation
322 GPUs each context has its own translation table, called Per-Process
323 Graphics Translation Table (PPGTT). Of important note, is that although
324 PPGTT is named per-process it is actually per context. When user space
325 submits a batchbuffer, the kernel walks the list of GEM buffer objects
326 used by the batchbuffer and guarantees that not only is the memory of
327 each such GEM buffer object resident but it is also present in the
328 (PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT,
329 then it is given an address. Two consequences of this are: the kernel
330 needs to edit the batchbuffer submitted to write the correct value of
331 the GPU address when a GEM BO is assigned a GPU address and the kernel
332 might evict a different GEM BO from the (PP)GTT to make address room
333 for another GEM BO. Consequently, the ioctls submitting a batchbuffer
334 for execution also include a list of all locations within buffers that
335 refer to GPU-addresses so that the kernel can edit the buffer correctly.
336 This process is dubbed relocation.
342 This is a description of how the locking should be after
343 refactoring is done. Does not necessarily reflect what the locking
344 looks like while WIP.
346 #. All locking rules and interface contracts with cross-driver interfaces
347 (dma-buf, dma_fence) need to be followed.
349 #. No struct_mutex anywhere in the code
351 #. dma_resv will be the outermost lock (when needed) and ww_acquire_ctx
352 is to be hoisted at highest level and passed down within i915_gem_ctx
355 #. While holding lru/memory manager (buddy, drm_mm, whatever) locks
356 system memory allocations are not allowed
358 * Enforce this by priming lockdep (with fs_reclaim). If we
359 allocate memory while holding these looks we get a rehash
360 of the shrinker vs. struct_mutex saga, and that would be
363 #. Do not nest different lru/memory manager locks within each other.
364 Take them in turn to update memory allocations, relying on the object’s
365 dma_resv ww_mutex to serialize against other operations.
367 #. The suggestion for lru/memory managers locks is that they are small
368 enough to be spinlocks.
370 #. All features need to come with exhaustive kernel selftests and/or
371 IGT tests when appropriate
373 #. All LMEM uAPI paths need to be fully restartable (_interruptible()
374 for all locks/waits/sleeps)
376 * Error handling validation through signal injection.
377 Still the best strategy we have for validating GEM uAPI
379 Must be excessively used in the IGT, and we need to check
380 that we really have full path coverage of all error cases.
382 * -EDEADLK handling with ww_mutex
384 GEM BO Management Implementation Details
385 ----------------------------------------
387 .. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h
388 :doc: Virtual Memory Address
390 Buffer Object Eviction
391 ----------------------
393 This section documents the interface functions for evicting buffer
394 objects to make space available in the virtual gpu address spaces. Note
395 that this is mostly orthogonal to shrinking buffer objects caches, which
396 has the goal to make main memory (shared with the gpu through the
397 unified memory architecture) available.
399 .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c
402 Buffer Object Memory Shrinking
403 ------------------------------
405 This section documents the interface function for shrinking memory usage
406 of buffer object caches. Shrinking is used to make main memory
407 available. Note that this is mostly orthogonal to evicting buffer
408 objects, which has the goal to make space in gpu virtual address spaces.
410 .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
416 .. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c
417 :doc: batch buffer command parser
419 .. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c
422 User Batchbuffer Execution
423 --------------------------
425 .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_context_types.h
427 .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
428 :doc: User command execution
432 .. kernel-doc:: drivers/gpu/drm/i915/i915_scheduler_types.h
433 :functions: i915_sched_engine
435 Logical Rings, Logical Ring Contexts and Execlists
436 --------------------------------------------------
438 .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_execlists_submission.c
439 :doc: Logical Rings, Logical Ring Contexts and Execlists
444 .. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h
445 :doc: Global GTT views
447 .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c
450 GTT Fences and Swizzling
451 ------------------------
453 .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
456 Global GTT Fence Handling
457 ~~~~~~~~~~~~~~~~~~~~~~~~~
459 .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
460 :doc: fence register handling
462 Hardware Tiling and Swizzling Details
463 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
465 .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
466 :doc: tiling swizzling details
471 .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c
474 .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c
475 :doc: buffer object tiling
480 .. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp.c
483 .. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp_types.h
488 Starting from gen9, three microcontrollers are available on the HW: the
489 graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the
490 display microcontroller (DMC). The driver is responsible for loading the
491 firmwares on the microcontrollers; the GuC and HuC firmwares are transferred
492 to WOPCM using the DMA engine, while the DMC firmware is written through MMIO.
500 .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_wopcm.c
506 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
509 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.h
514 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
515 :doc: Firmware Layout
517 GuC Memory Management
518 ~~~~~~~~~~~~~~~~~~~~~
520 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
521 :doc: GuC Memory Management
522 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
523 :functions: intel_guc_allocate_vma
526 GuC-specific firmware loader
527 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
529 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
532 GuC-based command submission
533 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
535 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
536 :doc: GuC-based command submission
539 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
541 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
542 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h
543 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
544 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
545 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
549 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
551 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
552 :functions: intel_huc_auth
554 HuC Memory Management
555 ~~~~~~~~~~~~~~~~~~~~~
557 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
558 :doc: HuC Memory Management
562 The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_
566 See `DMC Firmware Support`_
571 This sections covers all things related to the tracepoints implemented
574 i915_ppgtt_create and i915_ppgtt_release
575 ----------------------------------------
577 .. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
578 :doc: i915_ppgtt_create and i915_ppgtt_release tracepoints
580 i915_context_create and i915_context_free
581 -----------------------------------------
583 .. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
584 :doc: i915_context_create and i915_context_free tracepoints
591 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
592 :doc: i915 Perf Overview
594 Comparison with Core Perf
595 -------------------------
596 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
597 :doc: i915 Perf History and Comparison with Core Perf
599 i915 Driver Entry Points
600 ------------------------
602 This section covers the entrypoints exported outside of i915_perf.c to
603 integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl.
605 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
606 :functions: i915_perf_init
607 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
608 :functions: i915_perf_fini
609 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
610 :functions: i915_perf_register
611 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
612 :functions: i915_perf_unregister
613 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
614 :functions: i915_perf_open_ioctl
615 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
616 :functions: i915_perf_release
617 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
618 :functions: i915_perf_add_config_ioctl
619 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
620 :functions: i915_perf_remove_config_ioctl
625 This section covers the stream-semantics-agnostic structures and functions
626 for representing an i915 perf stream FD and associated file operations.
628 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h
629 :functions: i915_perf_stream
630 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h
631 :functions: i915_perf_stream_ops
633 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
634 :functions: read_properties_unlocked
635 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
636 :functions: i915_perf_open_ioctl_locked
637 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
638 :functions: i915_perf_destroy_locked
639 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
640 :functions: i915_perf_read
641 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
642 :functions: i915_perf_ioctl
643 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
644 :functions: i915_perf_enable_locked
645 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
646 :functions: i915_perf_disable_locked
647 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
648 :functions: i915_perf_poll
649 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
650 :functions: i915_perf_poll_locked
652 i915 Perf Observation Architecture Stream
653 -----------------------------------------
655 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h
656 :functions: i915_oa_ops
658 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
659 :functions: i915_oa_stream_init
660 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
661 :functions: i915_oa_read
662 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
663 :functions: i915_oa_stream_enable
664 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
665 :functions: i915_oa_stream_disable
666 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
667 :functions: i915_oa_wait_unlocked
668 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
669 :functions: i915_oa_poll_wait
671 Other i915 Perf Internals
672 -------------------------
674 This section simply includes all other currently documented i915 perf internals,
675 in no particular order, but may include some more minor utilities or platform
676 specific details than found in the more high-level sections.
678 .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
687 i915_perf_add_config_ioctl
688 i915_perf_remove_config_ioctl
689 read_properties_unlocked
690 i915_perf_open_ioctl_locked
691 i915_perf_destroy_locked
692 i915_perf_read i915_perf_ioctl
693 i915_perf_enable_locked
694 i915_perf_disable_locked
695 i915_perf_poll i915_perf_poll_locked
696 i915_oa_stream_init i915_oa_read
697 i915_oa_stream_enable
698 i915_oa_stream_disable
699 i915_oa_wait_unlocked
705 The drm/i915 driver codebase has some style rules in addition to (and, in some
706 cases, deviating from) the kernel coding style.
708 Register macro definition style
709 -------------------------------
711 The style guide for ``i915_reg.h``.
713 .. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h
714 :doc: The i915 register macro definition style guide
716 .. _i915-usage-stats:
718 i915 DRM client usage stats implementation
719 ==========================================
721 The drm/i915 driver implements the DRM client usage stats specification as
722 documented in :ref:`drm-client-usage-stats`.
724 Example of the output showing the implemented key value pairs and entirety of
725 the currently possible format options:
733 drm-pdev: 0000:00:02.0
735 drm-engine-render: 9288864723 ns
736 drm-engine-copy: 2035071108 ns
737 drm-engine-video: 0 ns
738 drm-engine-capacity-video: 2
739 drm-engine-video-enhance: 0 ns
741 Possible `drm-engine-` key names are: `render`, `copy`, `video` and