1 Buffer Sharing and Synchronization
2 ==================================
4 The dma-buf subsystem provides the framework for sharing buffers for
5 hardware (DMA) access across multiple device drivers and subsystems, and
6 for synchronizing asynchronous hardware access.
8 This is used, for example, by drm "prime" multi-GPU support, but is of
9 course not limited to GPU use cases.
11 The three main components of this are: (1) dma-buf, representing a
12 sg_table and exposed to userspace as a file descriptor to allow passing
13 between devices, (2) fence, which provides a mechanism to signal when
14 one device has finished access, and (3) reservation, which manages the
15 shared or exclusive fence(s) associated with the buffer.
20 This document serves as a guide to device-driver writers on what is the dma-buf
21 buffer sharing API, how to use it for exporting and using shared buffers.
23 Any device driver which wishes to be a part of DMA buffer sharing, can do so as
24 either the 'exporter' of buffers, or the 'user' or 'importer' of buffers.
26 Say a driver A wants to use buffers created by driver B, then we call B as the
27 exporter, and A as buffer-user/importer.
31 - implements and manages operations in :c:type:`struct dma_buf_ops
32 <dma_buf_ops>` for the buffer,
33 - allows other users to share the buffer by using dma_buf sharing APIs,
34 - manages the details of buffer allocation, wrapped in a :c:type:`struct
36 - decides about the actual backing storage where this allocation happens,
37 - and takes care of any migration of scatterlist - for all (shared) users of
42 - is one of (many) sharing users of the buffer.
43 - doesn't need to worry about how the buffer is allocated, or where.
44 - and needs a mechanism to get access to the scatterlist that makes up this
45 buffer in memory, mapped into its own address space, so it can access the
46 same area of memory. This interface is provided by :c:type:`struct
47 dma_buf_attachment <dma_buf_attachment>`.
49 Any exporters or users of the dma-buf buffer sharing framework must have a
50 'select DMA_SHARED_BUFFER' in their respective Kconfigs.
52 Userspace Interface Notes
53 ~~~~~~~~~~~~~~~~~~~~~~~~~
55 Mostly a DMA buffer file descriptor is simply an opaque object for userspace,
56 and hence the generic interface exposed is very minimal. There's a few things to
59 - Since kernel 3.12 the dma-buf FD supports the llseek system call, but only
60 with offset=0 and whence=SEEK_END|SEEK_SET. SEEK_SET is supported to allow
61 the usual size discover pattern size = SEEK_END(0); SEEK_SET(0). Every other
62 llseek operation will report -EINVAL.
64 If llseek on dma-buf FDs isn't support the kernel will report -ESPIPE for all
65 cases. Userspace can use this to detect support for discovering the dma-buf
68 - In order to avoid fd leaks on exec, the FD_CLOEXEC flag must be set
69 on the file descriptor. This is not just a resource leak, but a
70 potential security hole. It could give the newly exec'd application
71 access to buffers, via the leaked fd, to which it should otherwise
72 not be permitted access.
74 The problem with doing this via a separate fcntl() call, versus doing it
75 atomically when the fd is created, is that this is inherently racy in a
76 multi-threaded app[3]. The issue is made worse when it is library code
77 opening/creating the file descriptor, as the application may not even be
80 To avoid this problem, userspace must have a way to request O_CLOEXEC
81 flag be set when the dma-buf fd is created. So any API provided by
82 the exporting driver to create a dmabuf fd must provide a way to let
83 userspace control setting of O_CLOEXEC flag passed in to dma_buf_fd().
85 - Memory mapping the contents of the DMA buffer is also supported. See the
86 discussion below on `CPU Access to DMA Buffer Objects`_ for the full details.
88 - The DMA buffer FD is also pollable, see `Implicit Fence Poll Support`_ below for
91 Basic Operation and Device DMA Access
92 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
94 .. kernel-doc:: drivers/dma-buf/dma-buf.c
95 :doc: dma buf device access
97 CPU Access to DMA Buffer Objects
98 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
100 .. kernel-doc:: drivers/dma-buf/dma-buf.c
103 Implicit Fence Poll Support
104 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
106 .. kernel-doc:: drivers/dma-buf/dma-buf.c
107 :doc: implicit fence polling
111 .. kernel-doc:: drivers/dma-buf/dma-buf-sysfs-stats.c
114 Kernel Functions and Structures Reference
115 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
117 .. kernel-doc:: drivers/dma-buf/dma-buf.c
120 .. kernel-doc:: include/linux/dma-buf.h
123 Buffer Mapping Helpers
124 ~~~~~~~~~~~~~~~~~~~~~~
126 .. kernel-doc:: include/linux/dma-buf-map.h
129 .. kernel-doc:: include/linux/dma-buf-map.h
135 .. kernel-doc:: drivers/dma-buf/dma-resv.c
136 :doc: Reservation Object Overview
138 .. kernel-doc:: drivers/dma-buf/dma-resv.c
141 .. kernel-doc:: include/linux/dma-resv.h
147 .. kernel-doc:: drivers/dma-buf/dma-fence.c
148 :doc: DMA fences overview
150 DMA Fence Cross-Driver Contract
151 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
153 .. kernel-doc:: drivers/dma-buf/dma-fence.c
154 :doc: fence cross-driver contract
156 DMA Fence Signalling Annotations
157 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
159 .. kernel-doc:: drivers/dma-buf/dma-fence.c
160 :doc: fence signalling annotation
162 DMA Fences Functions Reference
163 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
165 .. kernel-doc:: drivers/dma-buf/dma-fence.c
168 .. kernel-doc:: include/linux/dma-fence.h
171 Seqno Hardware Fences
172 ~~~~~~~~~~~~~~~~~~~~~
174 .. kernel-doc:: include/linux/seqno-fence.h
180 .. kernel-doc:: drivers/dma-buf/dma-fence-array.c
183 .. kernel-doc:: include/linux/dma-fence-array.h
189 .. kernel-doc:: drivers/dma-buf/dma-fence-chain.c
192 .. kernel-doc:: include/linux/dma-fence-chain.h
195 DMA Fence uABI/Sync File
196 ~~~~~~~~~~~~~~~~~~~~~~~~
198 .. kernel-doc:: drivers/dma-buf/sync_file.c
201 .. kernel-doc:: include/linux/sync_file.h
204 Indefinite DMA Fences
205 ~~~~~~~~~~~~~~~~~~~~~
207 At various times struct dma_fence with an indefinite time until dma_fence_wait()
208 finishes have been proposed. Examples include:
210 * Future fences, used in HWC1 to signal when a buffer isn't used by the display
211 any longer, and created with the screen update that makes the buffer visible.
212 The time this fence completes is entirely under userspace's control.
214 * Proxy fences, proposed to handle &drm_syncobj for which the fence has not yet
215 been set. Used to asynchronously delay command submission.
217 * Userspace fences or gpu futexes, fine-grained locking within a command buffer
218 that userspace uses for synchronization across engines or with the CPU, which
219 are then imported as a DMA fence for integration into existing winsys
222 * Long-running compute command buffers, while still using traditional end of
223 batch DMA fences for memory management instead of context preemption DMA
224 fences which get reattached when the compute job is rescheduled.
226 Common to all these schemes is that userspace controls the dependencies of these
227 fences and controls when they fire. Mixing indefinite fences with normal
228 in-kernel DMA fences does not work, even when a fallback timeout is included to
229 protect against malicious userspace:
231 * Only the kernel knows about all DMA fence dependencies, userspace is not aware
232 of dependencies injected due to memory management or scheduler decisions.
234 * Only userspace knows about all dependencies in indefinite fences and when
235 exactly they will complete, the kernel has no visibility.
237 Furthermore the kernel has to be able to hold up userspace command submission
238 for memory management needs, which means we must support indefinite fences being
239 dependent upon DMA fences. If the kernel also support indefinite fences in the
240 kernel like a DMA fence, like any of the above proposal would, there is the
241 potential for deadlocks.
243 .. kernel-render:: DOT
244 :alt: Indefinite Fencing Dependency Cycle
245 :caption: Indefinite Fencing Dependency Cycle
247 digraph "Fencing Cycle" {
248 node [shape=box bgcolor=grey style=filled]
249 kernel [label="Kernel DMA Fences"]
250 userspace [label="userspace controlled fences"]
251 kernel -> userspace [label="memory management"]
252 userspace -> kernel [label="Future fence, fence proxy, ..."]
254 { rank=same; kernel userspace }
257 This means that the kernel might accidentally create deadlocks
258 through memory management dependencies which userspace is unaware of, which
259 randomly hangs workloads until the timeout kicks in. Workloads, which from
260 userspace's perspective, do not contain a deadlock. In such a mixed fencing
261 architecture there is no single entity with knowledge of all dependencies.
262 Thefore preventing such deadlocks from within the kernel is not possible.
264 The only solution to avoid dependencies loops is by not allowing indefinite
265 fences in the kernel. This means:
267 * No future fences, proxy fences or userspace fences imported as DMA fences,
268 with or without a timeout.
270 * No DMA fences that signal end of batchbuffer for command submission where
271 userspace is allowed to use userspace fencing or long running compute
272 workloads. This also means no implicit fencing for shared buffers in these
275 Recoverable Hardware Page Faults Implications
276 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
278 Modern hardware supports recoverable page faults, which has a lot of
279 implications for DMA fences.
281 First, a pending page fault obviously holds up the work that's running on the
282 accelerator and a memory allocation is usually required to resolve the fault.
283 But memory allocations are not allowed to gate completion of DMA fences, which
284 means any workload using recoverable page faults cannot use DMA fences for
285 synchronization. Synchronization fences controlled by userspace must be used
288 On GPUs this poses a problem, because current desktop compositor protocols on
289 Linux rely on DMA fences, which means without an entirely new userspace stack
290 built on top of userspace fences, they cannot benefit from recoverable page
291 faults. Specifically this means implicit synchronization will not be possible.
292 The exception is when page faults are only used as migration hints and never to
293 on-demand fill a memory request. For now this means recoverable page
294 faults on GPUs are limited to pure compute workloads.
296 Furthermore GPUs usually have shared resources between the 3D rendering and
297 compute side, like compute units or command submission engines. If both a 3D
298 job with a DMA fence and a compute workload using recoverable page faults are
299 pending they could deadlock:
301 - The 3D workload might need to wait for the compute job to finish and release
302 hardware resources first.
304 - The compute workload might be stuck in a page fault, because the memory
305 allocation is waiting for the DMA fence of the 3D workload to complete.
307 There are a few options to prevent this problem, one of which drivers need to
310 - Compute workloads can always be preempted, even when a page fault is pending
311 and not yet repaired. Not all hardware supports this.
313 - DMA fence workloads and workloads which need page fault handling have
314 independent hardware resources to guarantee forward progress. This could be
315 achieved through e.g. through dedicated engines and minimal compute unit
316 reservations for DMA fence workloads.
318 - The reservation approach could be further refined by only reserving the
319 hardware resources for DMA fence workloads when they are in-flight. This must
320 cover the time from when the DMA fence is visible to other threads up to
321 moment when fence is completed through dma_fence_signal().
323 - As a last resort, if the hardware provides no useful reservation mechanics,
324 all workloads must be flushed from the GPU when switching between jobs
325 requiring DMA fences or jobs requiring page fault handling: This means all DMA
326 fences must complete before a compute job with page fault handling can be
327 inserted into the scheduler queue. And vice versa, before a DMA fence can be
328 made visible anywhere in the system, all compute workloads must be preempted
329 to guarantee all pending GPU page faults are flushed.
331 - Only a fairly theoretical option would be to untangle these dependencies when
332 allocating memory to repair hardware page faults, either through separate
333 memory blocks or runtime tracking of the full dependency graph of all DMA
334 fences. This results very wide impact on the kernel, since resolving the page
335 on the CPU side can itself involve a page fault. It is much more feasible and
336 robust to limit the impact of handling hardware page faults to the specific
339 Note that workloads that run on independent hardware like copy engines or other
340 GPUs do not have any impact. This allows us to keep using DMA fences internally
341 in the kernel even for resolving hardware page faults, e.g. by using copy
342 engines to clear or copy memory needed to resolve the page fault.
344 In some ways this page fault problem is a special case of the `Infinite DMA
345 Fences` discussions: Infinite fences from compute workloads are allowed to
346 depend on DMA fences, but not the other way around. And not even the page fault
347 problem is new, because some other CPU thread in userspace might
348 hit a page fault which holds up a userspace fence - supporting page faults on
349 GPUs doesn't anything fundamentally new.