1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2020 MediaTek
5 $id: http://devicetree.org/schemas/usb/mediatek,musb.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek MUSB DRD/OTG Controller Device Tree Bindings
11 - Min Guo <min.guo@mediatek.com>
15 pattern: '^usb@[0-9a-f]+$'
20 - mediatek,mt8516-musb
21 - mediatek,mt2701-musb
22 - const: mediatek,mtk-musb
36 - description: The main/core clock
37 - description: The system bus clock
38 - description: The 48Mhz clock
50 $ref: /schemas/types.yaml#/definitions/flag
51 description: Support role switch. See usb/generic.txt
61 description: A phandle to USB power domain node to control USB's MTCMOS
65 $ref: /connector/usb-connector.yaml#
66 description: Connector for dual role switch
70 usb-role-switch: [ 'connector' ]
71 connector: [ 'usb-role-switch' ]
82 additionalProperties: false
86 #include <dt-bindings/clock/mt2701-clk.h>
87 #include <dt-bindings/gpio/gpio.h>
88 #include <dt-bindings/interrupt-controller/arm-gic.h>
89 #include <dt-bindings/interrupt-controller/irq.h>
90 #include <dt-bindings/phy/phy.h>
91 #include <dt-bindings/power/mt2701-power.h>
94 compatible = "mediatek,mt2701-musb", "mediatek,mtk-musb";
95 reg = <0x11200000 0x1000>;
96 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
97 interrupt-names = "mc";
98 phys = <&u2port2 PHY_TYPE_USB2>;
100 clocks = <&pericfg CLK_PERI_USB0>,
101 <&pericfg CLK_PERI_USB0_MCU>,
102 <&pericfg CLK_PERI_USB_SLV>;
103 clock-names = "main","mcu","univpll";
104 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
108 compatible = "gpio-usb-b-connector", "usb-b-connector";
110 id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>;
111 vbus-supply = <&usb_vbus>;