1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2020 MediaTek
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek USB3 xHCI Device Tree Bindings
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: "usb-xhci.yaml"
17 There are two scenarios:
18 case 1: only supports xHCI driver;
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
22 # common properties for both case 1 and case 2
26 - mediatek,mt2701-xhci
27 - mediatek,mt2712-xhci
28 - mediatek,mt7622-xhci
29 - mediatek,mt7623-xhci
30 - mediatek,mt7629-xhci
31 - mediatek,mt8173-xhci
32 - mediatek,mt8183-xhci
33 - mediatek,mt8192-xhci
34 - const: mediatek,mtk-xhci
39 - description: the registers of xHCI MAC
40 - description: the registers of IP Port Control
46 - const: ippc # optional, only needed for case 1.
50 use "interrupts-extended" when the interrupts are connected to the
51 separate interrupt controllers
54 - description: xHCI host controller interrupt
55 - description: optional, wakeup interrupt used to support runtime PM
63 description: A phandle to USB power domain node to control USB's MTCMOS
69 - description: Controller clock used by normal mode
70 - description: Reference clock used by low power mode etc
71 - description: Mcu bus clock for register access
72 - description: DMA bus clock for data transfer
73 - description: controller clock
78 - const: sys_ck # required, the following ones are optional
88 assigned-clock-parents:
94 List of all PHYs used on this HCD, it's better to keep PHYs in order
95 as the hardware layout
98 - description: USB2/HS PHY # required, others are optional
99 - description: USB3/SS(P) PHY
100 - description: USB2/HS PHY
101 - description: USB3/SS(P) PHY
102 - description: USB2/HS PHY
103 - description: USB3/SS(P) PHY
104 - description: USB2/HS PHY
105 - description: USB3/SS(P) PHY
106 - description: USB2/HS PHY
109 description: Regulator of USB AVDD3.3v
112 description: Regulator of USB VBUS5v
114 usb3-lpm-capable: true
116 usb2-lpm-disable: true
120 Interrupt moderation interval value, it is 8 times as much as that
121 defined in the xHCI spec on MTK's controller.
124 # the following properties are only used for case 1
126 description: enable USB remote wakeup, see power/wakeup-source.txt
129 mediatek,syscon-wakeup:
130 $ref: /schemas/types.yaml#/definitions/phandle-array
133 A phandle to syscon used to access the register of the USB wakeup glue
134 layer between xHCI and SPM, the field should always be 3 cells long.
138 The first cell represents a phandle to syscon
140 The second cell represents the register base address of the glue
143 The third cell represents the hardware version of the glue layer,
144 1 - used by mt8173 etc, revision 1 without following IPM rule;
145 2 - used by mt2712 etc, revision 2 following IPM rule;
146 101 - used by mt8183, specific 1.01;
147 102 - used by mt8192, specific 1.02;
148 enum: [1, 2, 101, 102]
150 mediatek,u3p-dis-msk:
151 $ref: /schemas/types.yaml#/definitions/uint32
152 description: The mask to disable u3ports, bit0 for u3port0,
153 bit1 for u3port1, ... etc
164 description: The hard wired USB devices.
167 wakeup-source: [ 'mediatek,syscon-wakeup' ]
177 additionalProperties: false
181 #include <dt-bindings/clock/mt8173-clk.h>
182 #include <dt-bindings/interrupt-controller/arm-gic.h>
183 #include <dt-bindings/interrupt-controller/irq.h>
184 #include <dt-bindings/phy/phy.h>
185 #include <dt-bindings/power/mt8173-power.h>
188 compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
189 reg = <0x11270000 0x1000>, <0x11280700 0x0100>;
190 reg-names = "mac", "ippc";
191 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
192 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
193 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
194 clock-names = "sys_ck", "ref_ck";
195 phys = <&u3port0 PHY_TYPE_USB3>, <&u2port1 PHY_TYPE_USB2>;
196 vusb33-supply = <&mt6397_vusb_reg>;
197 vbus-supply = <&usb_p1_vbus>;
198 imod-interval-ns = <10000>;
199 mediatek,syscon-wakeup = <&pericfg 0x400 1>;