1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 # Copyright 2019 Linaro Ltd.
5 $id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: QCOM SoC Temperature Sensor (TSENS)
11 - Amit Kucheria <amitk@kernel.org>
14 QCOM SoCs have TSENS IP to allow temperature measurement. There are currently
15 three distinct major versions of the IP that is supported by a single driver.
16 The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures
17 everything before v1 when there was no versioning information.
22 - description: msm9860 TSENS based
27 - description: v0.1 of TSENS
34 - const: qcom,tsens-v0_1
36 - description: v1 of TSENS
41 - const: qcom,tsens-v1
43 - description: v2 of TSENS
56 - const: qcom,tsens-v2
60 - description: TM registers
61 - description: SROT registers
66 - description: Combined interrupt if upper or lower threshold crossed
67 - description: Interrupt if critical threshold crossed
79 Reference to an nvmem node for the calibration data
91 Number of sensors enabled on this platform
92 $ref: /schemas/types.yaml#/definitions/uint32
96 "#thermal-sensor-cells":
99 Number of cells required to uniquely identify the thermal sensors. Since
100 we have multiple sensors this is set to 1
106 - "#thermal-sensor-cells"
150 additionalProperties: false
154 #include <dt-bindings/interrupt-controller/arm-gic.h>
155 // Example msm9860 based SoC (ipq8064):
156 gcc: clock-controller {
160 tsens: thermal-sensor {
161 compatible = "qcom,ipq8064-tsens";
163 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
164 nvmem-cell-names = "calib", "calib_backup";
165 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
166 interrupt-names = "uplow";
168 #qcom,sensors = <11>;
169 #thermal-sensor-cells = <1>;
174 #include <dt-bindings/interrupt-controller/arm-gic.h>
175 // Example 1 (legacy: for pre v1 IP):
176 tsens1: thermal-sensor@900000 {
177 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
178 reg = <0x4a9000 0x1000>, /* TM */
179 <0x4a8000 0x1000>; /* SROT */
181 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
182 nvmem-cell-names = "calib", "calib_sel";
184 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
185 interrupt-names = "uplow";
188 #thermal-sensor-cells = <1>;
192 #include <dt-bindings/interrupt-controller/arm-gic.h>
193 // Example 2 (for any platform containing v1 of the TSENS IP):
194 tsens2: thermal-sensor@4a9000 {
195 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
196 reg = <0x004a9000 0x1000>, /* TM */
197 <0x004a8000 0x1000>; /* SROT */
199 nvmem-cells = <&tsens_caldata>;
200 nvmem-cell-names = "calib";
202 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
203 interrupt-names = "uplow";
205 #qcom,sensors = <10>;
206 #thermal-sensor-cells = <1>;
210 #include <dt-bindings/interrupt-controller/arm-gic.h>
211 // Example 3 (for any platform containing v2 of the TSENS IP):
212 tsens3: thermal-sensor@c263000 {
213 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
214 reg = <0xc263000 0x1ff>,
217 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
219 interrupt-names = "uplow", "critical";
221 #qcom,sensors = <13>;
222 #thermal-sensor-cells = <1>;