1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Controller Common Properties
10 - Mark Brown <broonie@kernel.org>
13 SPI busses can be described with a node for the SPI controller device
14 and a set of child nodes for each SPI slave on the bus. The system SPI
15 controller may be described for use in SPI master mode or in SPI slave mode,
16 but not for both at the same time.
20 pattern: "^spi(@.*|-([0-9]|[1-9][0-9]+))?$"
30 GPIOs used as chip selects.
31 If that property is used, the number of chip selects will be
32 increased automatically with max(cs-gpios, hardware chip selects).
34 So if, for example, the controller has 4 CS lines, and the
35 cs-gpios looks like this
36 cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
38 Then it should be configured so that num_chipselect = 4, with
45 The second flag of a gpio descriptor can be GPIO_ACTIVE_HIGH (0)
46 or GPIO_ACTIVE_LOW(1). Legacy device trees often use 0.
48 There is a special rule set for combining the second flag of an
49 cs-gpio with the optional spi-cs-high flag for SPI slaves.
51 Each table entry defines how the CS pin is to be physically
52 driven (not considering potential gpio inversions by pinmux):
54 device node | cs-gpio | CS pin state active | Note
55 ================+===============+=====================+=====
58 spi-cs-high | ACTIVE_HIGH | H |
59 - | ACTIVE_HIGH | L | 1
60 spi-cs-high | ACTIVE_LOW | H | 2
64 1) Should print a warning about polarity inversion.
65 Here it would be wise to avoid and define the gpio as
67 2) Should print a warning about polarity inversion
68 because ACTIVE_LOW is overridden by spi-cs-high.
69 Should be generally avoided and be replaced by
70 spi-cs-high + ACTIVE_HIGH.
73 $ref: /schemas/types.yaml#/definitions/uint32
75 Size of the RX and TX data FIFOs in bytes.
78 $ref: /schemas/types.yaml#/definitions/uint32
80 Size of the RX data FIFO in bytes.
83 $ref: /schemas/types.yaml#/definitions/uint32
85 Size of the TX data FIFO in bytes.
88 $ref: /schemas/types.yaml#/definitions/uint32
90 Total number of chip selects.
93 $ref: /schemas/types.yaml#/definitions/flag
95 The SPI controller acts as a slave, instead of a master.
103 Compatible of the SPI device.
111 $ref: spi-peripheral-props.yaml
112 additionalProperties: true
116 $ref: /schemas/types.yaml#/definitions/flag
118 The device requires 3-wire mode.
121 $ref: /schemas/types.yaml#/definitions/flag
123 The device requires shifted clock phase (CPHA) mode.
126 $ref: /schemas/types.yaml#/definitions/flag
128 The device requires inverse clock polarity (CPOL) mode.
135 rx-fifo-depth: [ tx-fifo-depth ]
136 tx-fifo-depth: [ rx-fifo-depth ]
160 additionalProperties: true
165 #address-cells = <1>;
167 compatible = "fsl,imx28-spi";
168 reg = <0x80010000 0x2000>;
170 dmas = <&dma_apbh 0>;
174 compatible = "lg,lg4573";
175 spi-max-frequency = <1000000>;
180 compatible = "bosch,bme680";
181 spi-max-frequency = <100000>;
186 compatible = "jedec,spi-nor";
187 spi-max-frequency = <50000000>;
189 stacked-memories = /bits/ 64 <0x10000000 0x10000000>;