Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Renesas MSIOF SPI controller
   8
   9 maintainers:
  10   - Geert Uytterhoeven <geert+renesas@glider.be>
  11
  12 allOf:
  13   - $ref: spi-controller.yaml#
  14
  15 properties:
  16   compatible:
  17     oneOf:
  18       - items:
  19           - const: renesas,msiof-sh73a0     # SH-Mobile AG5
  20           - const: renesas,sh-mobile-msiof  # generic SH-Mobile compatible
  21                                             # device
  22       - items:
  23           - enum:
  24               - renesas,msiof-r8a7742       # RZ/G1H
  25               - renesas,msiof-r8a7743       # RZ/G1M
  26               - renesas,msiof-r8a7744       # RZ/G1N
  27               - renesas,msiof-r8a7745       # RZ/G1E
  28               - renesas,msiof-r8a77470      # RZ/G1C
  29               - renesas,msiof-r8a7790       # R-Car H2
  30               - renesas,msiof-r8a7791       # R-Car M2-W
  31               - renesas,msiof-r8a7792       # R-Car V2H
  32               - renesas,msiof-r8a7793       # R-Car M2-N
  33               - renesas,msiof-r8a7794       # R-Car E2
  34           - const: renesas,rcar-gen2-msiof  # generic R-Car Gen2 and RZ/G1
  35                                             # compatible device
  36       - items:
  37           - enum:
  38               - renesas,msiof-r8a774a1      # RZ/G2M
  39               - renesas,msiof-r8a774b1      # RZ/G2N
  40               - renesas,msiof-r8a774c0      # RZ/G2E
  41               - renesas,msiof-r8a774e1      # RZ/G2H
  42               - renesas,msiof-r8a7795       # R-Car H3
  43               - renesas,msiof-r8a7796       # R-Car M3-W
  44               - renesas,msiof-r8a77961      # R-Car M3-W+
  45               - renesas,msiof-r8a77965      # R-Car M3-N
  46               - renesas,msiof-r8a77970      # R-Car V3M
  47               - renesas,msiof-r8a77980      # R-Car V3H
  48               - renesas,msiof-r8a77990      # R-Car E3
  49               - renesas,msiof-r8a77995      # R-Car D3
  50               - renesas,msiof-r8a779a0      # R-Car V3U
  51           - const: renesas,rcar-gen3-msiof  # generic R-Car Gen3 and RZ/G2
  52                                             # compatible device
  53       - items:
  54           - const: renesas,sh-msiof  # deprecated
  55
  56   reg:
  57     minItems: 1
  58     maxItems: 2
  59     oneOf:
  60       - items:
  61           - description: CPU and DMA engine registers
  62       - items:
  63           - description: CPU registers
  64           - description: DMA engine registers
  65
  66   interrupts:
  67     maxItems: 1
  68
  69   clocks:
  70     maxItems: 1
  71
  72   num-cs:
  73     description: |
  74       Total number of chip selects (default is 1).
  75       Up to 3 native chip selects are supported:
  76         0: MSIOF_SYNC
  77         1: MSIOF_SS1
  78         2: MSIOF_SS2
  79       Hardware limitations related to chip selects:
  80         - Native chip selects are always deasserted in between transfers
  81           that are part of the same message.  Use cs-gpios to work around
  82           this.
  83         - All slaves using native chip selects must use the same spi-cs-high
  84           configuration.  Use cs-gpios to work around this.
  85         - When using GPIO chip selects, at least one native chip select must
  86           be left unused, as it will be driven anyway.
  87     minimum: 1
  88     maximum: 3
  89     default: 1
  90
  91   dmas:
  92     minItems: 2
  93     maxItems: 4
  94
  95   dma-names:
  96     minItems: 2
  97     maxItems: 4
  98     items:
  99       enum: [ tx, rx ]
 100
 101   renesas,dtdl:
 102     description: delay sync signal (setup) in transmit mode.
 103     $ref: /schemas/types.yaml#/definitions/uint32
 104     enum:
 105       - 0        # no bit delay
 106       - 50       # 0.5-clock-cycle delay
 107       - 100      # 1-clock-cycle delay
 108       - 150      # 1.5-clock-cycle delay
 109       - 200      # 2-clock-cycle delay
 110
 111   renesas,syncdl:
 112     description: delay sync signal (hold) in transmit mode
 113     $ref: /schemas/types.yaml#/definitions/uint32
 114     enum:
 115       - 0        # no bit delay
 116       - 50       # 0.5-clock-cycle delay
 117       - 100      # 1-clock-cycle delay
 118       - 150      # 1.5-clock-cycle delay
 119       - 200      # 2-clock-cycle delay
 120       - 300      # 3-clock-cycle delay
 121
 122   renesas,tx-fifo-size:
 123     # deprecated for soctype-specific bindings
 124     description: |
 125       Override the default TX fifo size.  Unit is words.  Ignored if 0.
 126     $ref: /schemas/types.yaml#/definitions/uint32
 127     maxItems: 1
 128     default: 64
 129
 130   renesas,rx-fifo-size:
 131     # deprecated for soctype-specific bindings
 132     description: |
 133       Override the default RX fifo size.  Unit is words.  Ignored if 0.
 134     $ref: /schemas/types.yaml#/definitions/uint32
 135     maxItems: 1
 136     default: 64
 137
 138 required:
 139   - compatible
 140   - reg
 141   - interrupts
 142   - '#address-cells'
 143   - '#size-cells'
 144
 145 unevaluatedProperties: false
 146
 147 examples:
 148   - |
 149     #include <dt-bindings/clock/r8a7791-clock.h>
 150     #include <dt-bindings/interrupt-controller/irq.h>
 151
 152     msiof0: spi@e6e20000 {
 153         compatible = "renesas,msiof-r8a7791", "renesas,rcar-gen2-msiof";
 154         reg = <0xe6e20000 0x0064>;
 155         interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
 156         clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
 157         dmas = <&dmac0 0x51>, <&dmac0 0x52>;
 158         dma-names = "tx", "rx";
 159         #address-cells = <1>;
 160         #size-cells = <0>;
 161     };