Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Renesas MSIOF SPI controller
   8
   9 maintainers:
  10   - Geert Uytterhoeven <geert+renesas@glider.be>
  11
  12 allOf:
  13   - $ref: spi-controller.yaml#
  14
  15 properties:
  16   compatible:
  17     oneOf:
  18       - items:
  19           - const: renesas,msiof-sh73a0     # SH-Mobile AG5
  20           - const: renesas,sh-mobile-msiof  # generic SH-Mobile compatible
  21                                             # device
  22       - items:
  23           - enum:
  24               - renesas,msiof-r8a7742       # RZ/G1H
  25               - renesas,msiof-r8a7743       # RZ/G1M
  26               - renesas,msiof-r8a7744       # RZ/G1N
  27               - renesas,msiof-r8a7745       # RZ/G1E
  28               - renesas,msiof-r8a77470      # RZ/G1C
  29               - renesas,msiof-r8a7790       # R-Car H2
  30               - renesas,msiof-r8a7791       # R-Car M2-W
  31               - renesas,msiof-r8a7792       # R-Car V2H
  32               - renesas,msiof-r8a7793       # R-Car M2-N
  33               - renesas,msiof-r8a7794       # R-Car E2
  34           - const: renesas,rcar-gen2-msiof  # generic R-Car Gen2 and RZ/G1
  35                                             # compatible device
  36       - items:
  37           - enum:
  38               - renesas,msiof-r8a774a1      # RZ/G2M
  39               - renesas,msiof-r8a774b1      # RZ/G2N
  40               - renesas,msiof-r8a774c0      # RZ/G2E
  41               - renesas,msiof-r8a774e1      # RZ/G2H
  42               - renesas,msiof-r8a7795       # R-Car H3
  43               - renesas,msiof-r8a7796       # R-Car M3-W
  44               - renesas,msiof-r8a77961      # R-Car M3-W+
  45               - renesas,msiof-r8a77965      # R-Car M3-N
  46               - renesas,msiof-r8a77970      # R-Car V3M
  47               - renesas,msiof-r8a77980      # R-Car V3H
  48               - renesas,msiof-r8a77990      # R-Car E3
  49               - renesas,msiof-r8a77995      # R-Car D3
  50           - const: renesas,rcar-gen3-msiof  # generic R-Car Gen3 and RZ/G2
  51                                             # compatible device
  52       - items:
  53           - const: renesas,sh-msiof  # deprecated
  54
  55   reg:
  56     minItems: 1
  57     maxItems: 2
  58     oneOf:
  59       - items:
  60           - description: CPU and DMA engine registers
  61       - items:
  62           - description: CPU registers
  63           - description: DMA engine registers
  64
  65   interrupts:
  66     maxItems: 1
  67
  68   clocks:
  69     maxItems: 1
  70
  71   num-cs:
  72     description: |
  73       Total number of chip selects (default is 1).
  74       Up to 3 native chip selects are supported:
  75         0: MSIOF_SYNC
  76         1: MSIOF_SS1
  77         2: MSIOF_SS2
  78       Hardware limitations related to chip selects:
  79         - Native chip selects are always deasserted in between transfers
  80           that are part of the same message.  Use cs-gpios to work around
  81           this.
  82         - All slaves using native chip selects must use the same spi-cs-high
  83           configuration.  Use cs-gpios to work around this.
  84         - When using GPIO chip selects, at least one native chip select must
  85           be left unused, as it will be driven anyway.
  86     minimum: 1
  87     maximum: 3
  88     default: 1
  89
  90   dmas:
  91     minItems: 2
  92     maxItems: 4
  93
  94   dma-names:
  95     minItems: 2
  96     maxItems: 4
  97     items:
  98       enum: [ tx, rx ]
  99
 100   renesas,dtdl:
 101     description: delay sync signal (setup) in transmit mode.
 102     $ref: /schemas/types.yaml#/definitions/uint32
 103     enum:
 104       - 0        # no bit delay
 105       - 50       # 0.5-clock-cycle delay
 106       - 100      # 1-clock-cycle delay
 107       - 150      # 1.5-clock-cycle delay
 108       - 200      # 2-clock-cycle delay
 109
 110   renesas,syncdl:
 111     description: delay sync signal (hold) in transmit mode
 112     $ref: /schemas/types.yaml#/definitions/uint32
 113     enum:
 114       - 0        # no bit delay
 115       - 50       # 0.5-clock-cycle delay
 116       - 100      # 1-clock-cycle delay
 117       - 150      # 1.5-clock-cycle delay
 118       - 200      # 2-clock-cycle delay
 119       - 300      # 3-clock-cycle delay
 120
 121   renesas,tx-fifo-size:
 122     # deprecated for soctype-specific bindings
 123     description: |
 124       Override the default TX fifo size.  Unit is words.  Ignored if 0.
 125     $ref: /schemas/types.yaml#/definitions/uint32
 126     maxItems: 1
 127     default: 64
 128
 129   renesas,rx-fifo-size:
 130     # deprecated for soctype-specific bindings
 131     description: |
 132       Override the default RX fifo size.  Unit is words.  Ignored if 0.
 133     $ref: /schemas/types.yaml#/definitions/uint32
 134     maxItems: 1
 135     default: 64
 136
 137 required:
 138   - compatible
 139   - reg
 140   - interrupts
 141   - '#address-cells'
 142   - '#size-cells'
 143
 144 examples:
 145   - |
 146     #include <dt-bindings/clock/r8a7791-clock.h>
 147     #include <dt-bindings/interrupt-controller/irq.h>
 148
 149     msiof0: spi@e6e20000 {
 150         compatible = "renesas,msiof-r8a7791", "renesas,rcar-gen2-msiof";
 151         reg = <0xe6e20000 0x0064>;
 152         interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
 153         clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
 154         dmas = <&dmac0 0x51>, <&dmac0 0x52>;
 155         dma-names = "tx", "rx";
 156         #address-cells = <1>;
 157         #size-cells = <0>;
 158     };