Documentation/devicetree/bindings/sound/mt8195-afe-pcm.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/sound/mt8195-afe-pcm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Mediatek AFE PCM controller for mt8195
   8
   9 maintainers:
  10   - Trevor Wu <trevor.wu@mediatek.com>
  11
  12 properties:
  13   compatible:
  14     const: mediatek,mt8195-audio
  15
  16   reg:
  17     maxItems: 1
  18
  19   interrupts:
  20     maxItems: 1
  21
  22   mediatek,topckgen:
  23     $ref: "/schemas/types.yaml#/definitions/phandle"
  24     description: The phandle of the mediatek topckgen controller
  25
  26   power-domains:
  27     maxItems: 1
  28
  29   clocks:
  30     items:
  31       - description: 26M clock
  32       - description: audio pll1 clock
  33       - description: audio pll2 clock
  34       - description: clock divider for i2si1_mck
  35       - description: clock divider for i2si2_mck
  36       - description: clock divider for i2so1_mck
  37       - description: clock divider for i2so2_mck
  38       - description: clock divider for dptx_mck
  39       - description: a1sys hoping clock
  40       - description: audio intbus clock
  41       - description: audio hires clock
  42       - description: audio local bus clock
  43       - description: mux for dptx_mck
  44       - description: mux for i2so1_mck
  45       - description: mux for i2so2_mck
  46       - description: mux for i2si1_mck
  47       - description: mux for i2si2_mck
  48       - description: audio infra 26M clock
  49       - description: infra bus clock
  50
  51   clock-names:
  52     items:
  53       - const: clk26m
  54       - const: apll1_ck
  55       - const: apll2_ck
  56       - const: apll12_div0
  57       - const: apll12_div1
  58       - const: apll12_div2
  59       - const: apll12_div3
  60       - const: apll12_div9
  61       - const: a1sys_hp_sel
  62       - const: aud_intbus_sel
  63       - const: audio_h_sel
  64       - const: audio_local_bus_sel
  65       - const: dptx_m_sel
  66       - const: i2so1_m_sel
  67       - const: i2so2_m_sel
  68       - const: i2si1_m_sel
  69       - const: i2si2_m_sel
  70       - const: infra_ao_audio_26m_b
  71       - const: scp_adsp_audiodsp
  72
  73   mediatek,etdm-in1-chn-disabled:
  74     $ref: /schemas/types.yaml#/definitions/uint8-array
  75     maxItems: 24
  76     description: Specify which input channel should be disabled.
  77
  78   mediatek,etdm-in2-chn-disabled:
  79     $ref: /schemas/types.yaml#/definitions/uint8-array
  80     maxItems: 16
  81     description: Specify which input channel should be disabled.
  82
  83 patternProperties:
  84   "^mediatek,etdm-in[1-2]-mclk-always-on-rate-hz$":
  85     description: Specify etdm in mclk output rate for always on case.
  86
  87   "^mediatek,etdm-out[1-3]-mclk-always-on-rate-hz$":
  88     description: Specify etdm out mclk output rate for always on case.
  89
  90   "^mediatek,etdm-in[1-2]-multi-pin-mode$":
  91     type: boolean
  92     description: if present, the etdm data mode is I2S.
  93
  94   "^mediatek,etdm-out[1-3]-multi-pin-mode$":
  95     type: boolean
  96     description: if present, the etdm data mode is I2S.
  97
  98   "^mediatek,etdm-in[1-2]-cowork-source$":
  99     $ref: /schemas/types.yaml#/definitions/uint32
 100     description: |
 101       etdm modules can share the same external clock pin. Specify
 102       which etdm clock source is required by this etdm in moudule.
 103     enum:
 104       - 0 # etdm1_in
 105       - 1 # etdm2_in
 106       - 2 # etdm1_out
 107       - 3 # etdm2_out
 108
 109   "^mediatek,etdm-out[1-2]-cowork-source$":
 110     $ref: /schemas/types.yaml#/definitions/uint32
 111     description: |
 112       etdm modules can share the same external clock pin. Specify
 113       which etdm clock source is required by this etdm out moudule.
 114     enum:
 115       - 0 # etdm1_in
 116       - 1 # etdm2_in
 117       - 2 # etdm1_out
 118       - 3 # etdm2_out
 119
 120 required:
 121   - compatible
 122   - reg
 123   - interrupts
 124   - mediatek,topckgen
 125   - power-domains
 126   - clocks
 127   - clock-names
 128
 129 additionalProperties: false
 130
 131 examples:
 132   - |
 133     #include <dt-bindings/clock/mt8195-clk.h>
 134     #include <dt-bindings/interrupt-controller/arm-gic.h>
 135     #include <dt-bindings/interrupt-controller/irq.h>
 136     #include <dt-bindings/power/mt8195-power.h>
 137
 138     afe: mt8195-afe-pcm@10890000 {
 139         compatible = "mediatek,mt8195-audio";
 140         reg = <0x10890000 0x10000>;
 141         interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
 142         mediatek,topckgen = <&topckgen>;
 143         power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
 144         clocks = <&clk26m>,
 145                  <&topckgen CLK_TOP_APLL1>,
 146                  <&topckgen CLK_TOP_APLL2>,
 147                  <&topckgen CLK_TOP_APLL12_DIV0>,
 148                  <&topckgen CLK_TOP_APLL12_DIV1>,
 149                  <&topckgen CLK_TOP_APLL12_DIV2>,
 150                  <&topckgen CLK_TOP_APLL12_DIV3>,
 151                  <&topckgen CLK_TOP_APLL12_DIV9>,
 152                  <&topckgen CLK_TOP_A1SYS_HP_SEL>,
 153                  <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
 154                  <&topckgen CLK_TOP_AUDIO_H_SEL>,
 155                  <&topckgen CLK_TOP_AUDIO_LOCAL_BUS_SEL>,
 156                  <&topckgen CLK_TOP_DPTX_M_SEL>,
 157                  <&topckgen CLK_TOP_I2SO1_M_SEL>,
 158                  <&topckgen CLK_TOP_I2SO2_M_SEL>,
 159                  <&topckgen CLK_TOP_I2SI1_M_SEL>,
 160                  <&topckgen CLK_TOP_I2SI2_M_SEL>,
 161                  <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
 162                  <&scp_adsp CLK_SCP_ADSP_AUDIODSP>;
 163         clock-names = "clk26m",
 164                       "apll1_ck",
 165                       "apll2_ck",
 166                       "apll12_div0",
 167                       "apll12_div1",
 168                       "apll12_div2",
 169                       "apll12_div3",
 170                       "apll12_div9",
 171                       "a1sys_hp_sel",
 172                       "aud_intbus_sel",
 173                       "audio_h_sel",
 174                       "audio_local_bus_sel",
 175                       "dptx_m_sel",
 176                       "i2so1_m_sel",
 177                       "i2so2_m_sel",
 178                       "i2si1_m_sel",
 179                       "i2si2_m_sel",
 180                       "infra_ao_audio_26m_b",
 181                       "scp_adsp_audiodsp";
 182     };
 183
 184 ...