1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/soc/ti/ti,pruss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
19 instruction RAMs, some internal peripheral modules to facilitate industrial
20 communication, and an interrupt controller.
22 The programmable nature of the PRUs provide flexibility to implement custom
23 peripheral interfaces, fast real-time responses, or specialized data handling.
24 The common peripheral modules include the following,
25 - an Ethernet MII_RT module with two MII ports
26 - an MDIO port to control external Ethernet PHYs
27 - an Industrial Ethernet Peripheral (IEP) to manage/generate Industrial
29 - an Enhanced Capture Module (eCAP)
30 - an Industrial Ethernet Timer with 7/9 capture and 16 compare events
31 - a 16550-compatible UART to support PROFIBUS
32 - Enhanced GPIO with async capture and serial support
34 A PRU-ICSS subsystem can have up to three shared data memories. A PRU core
35 acts on a primary Data RAM (there are usually 2 Data RAMs) at its address
36 0x0, but also has access to a secondary Data RAM (primary to the other PRU
37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed
38 by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are
39 common to both the PRU cores. Each PRU core also has a private instruction
40 RAM, and specific register spaces for Control and Debug functionalities.
42 Various sub-modules within a PRU-ICSS subsystem are represented as individual
43 nodes and are defined using a parent-child hierarchy depending on their
44 integration within the IP and the SoC. These nodes are described in the
50 Each PRU-ICSS instance is represented as its own node with the individual PRU
51 processor cores, the memories node, an INTC node and an MDIO node represented
52 as child nodes within this PRUSS node. This node shall be a child of the
53 corresponding interconnect bus nodes or target-module nodes.
55 See ../../mfd/syscon.yaml for generic SysCon binding details.
60 pattern: "^(pruss|icssg)@[0-9a-f]+$"
64 - ti,am3356-pruss # for AM335x SoC family
65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
66 - ti,am4376-pruss1 # for AM437x SoC family and PRUSS unit 1
67 - ti,am5728-pruss # for AM57xx SoC family
68 - ti,k2g-pruss # for 66AK2G SoC family
69 - ti,am654-icssg # for K3 AM65x SoC family
70 - ti,j721e-icssg # for K3 J721E SoC family
89 This property is as per sci-pm-domain.txt.
95 The various Data RAMs within a single PRU-ICSS unit are represented as a
96 single node with the name 'memories'.
102 minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM.
105 - description: Address and size of the Data RAM0.
106 - description: Address and size of the Data RAM1.
108 Address and size of the Shared Data RAM. Note that on AM437x one
109 of two PRUSS units don't contain Shared RAM, while the second one
124 additionalProperties: false
128 PRU-ICSS configuration space. CFG sub-module represented as a SysCon.
135 - const: ti,pruss-cfg
161 coreclk-mux@[a-f0-9]+$:
163 This is applicable only for ICSSG (K3 SoCs). The ICSSG modules
164 core clock can be set to one of the 2 sources: ICSSG_CORE_CLK or
165 ICSSG_ICLK. This node models this clock mux and should have the
176 - description: ICSSG_CORE Clock
177 - description: ICSSG_ICLK Clock
182 assigned-clock-parents:
185 Standard assigned-clocks-parents definition used for selecting
186 mux parent (one of the mux input).
194 additionalProperties: false
196 iepclk-mux@[a-f0-9]+$:
198 The IEP module can get its clock from 2 sources: ICSSG_IEP_CLK or
199 CORE_CLK (OCP_CLK in older SoCs). This node models this clock
200 mux and should have the name "iepclk-mux".
210 - description: ICSSG_IEP Clock
211 - description: Core Clock (OCP Clock in older SoCs)
216 assigned-clock-parents:
219 Standard assigned-clocks-parents definition used for selecting
220 mux parent (one of the mux input).
228 additionalProperties: false
230 additionalProperties: false
234 Industrial Ethernet Peripheral to manage/generate Industrial Ethernet
235 functions such as time stamping. Each PRUSS has either 1 IEP (on AM335x,
236 AM437x, AM57xx & 66AK2G SoCs) or 2 IEPs (on K3 AM65x & J721E SoCs ). IEP
237 is used for creating PTP clocks and generating PPS signals.
243 Real-Time Ethernet to support multiple industrial communication protocols.
244 MII-RT sub-module represented as a SysCon.
251 - const: ti,pruss-mii
257 additionalProperties: false
261 The Real-time Media Independent Interface to support multiple industrial
262 communication protocols (G stands for Gigabit). MII-G-RT sub-module
263 represented as a SysCon.
270 - const: ti,pruss-mii-g
276 additionalProperties: false
278 interrupt-controller@[a-f0-9]+$:
280 PRUSS INTC Node. Each PRUSS has a single interrupt controller instance
281 that is common to all the PRU cores. This should be represented as an
282 interrupt-controller node.
285 - $ref: /schemas/interrupt-controller/ti,pruss-intc.yaml#
291 MDIO Node. Each PRUSS has an MDIO module that can be used to control
292 external PHYs. The MDIO module used within the PRU-ICSS is an instance of
293 the MDIO Controller used in TI Davinci SoCs.
296 - $ref: /schemas/net/ti,davinci-mdio.yaml#
300 "^(pru|rtu|txpru)@[0-9a-f]+$":
302 PRU Node. Each PRUSS has dual PRU cores, each represented as a RemoteProc
303 device through a PRU child node each. Each node can optionally be rendered
304 inactive by using the standard DT string property, "status". The ICSSG IP
305 present on K3 SoCs have additional auxiliary PRU cores with slightly
306 different IP integration.
309 - $ref: /schemas/remoteproc/ti,pru-rproc.yaml#
318 additionalProperties: false
320 # Due to inability of correctly verifying sub-nodes with an @address through
321 # the "required" list, the required sub-nodes below are commented out for now.
325 # - interrupt-controller
343 /* Example 1 AM33xx PRU-ICSS */
345 compatible = "ti,am3356-pruss";
347 #address-cells = <1>;
351 pruss_mem: memories@0 {
355 reg-names = "dram0", "dram1", "shrdram2";
358 pruss_cfg: cfg@26000 {
359 compatible = "ti,pruss-cfg", "syscon";
360 #address-cells = <1>;
362 reg = <0x26000 0x2000>;
363 ranges = <0x00 0x26000 0x2000>;
366 #address-cells = <1>;
369 pruss_iepclk_mux: iepclk-mux@30 {
372 clocks = <&l3_gclk>, /* icss_iep */
373 <&pruss_ocp_gclk>; /* icss_ocp */
378 pruss_mii_rt: mii-rt@32000 {
379 compatible = "ti,pruss-mii", "syscon";
380 reg = <0x32000 0x58>;
383 pruss_intc: interrupt-controller@20000 {
384 compatible = "ti,pruss-intc";
385 reg = <0x20000 0x2000>;
386 interrupt-controller;
387 #interrupt-cells = <3>;
388 interrupts = <20 21 22 23 24 25 26 27>;
389 interrupt-names = "host_intr0", "host_intr1",
390 "host_intr2", "host_intr3",
391 "host_intr4", "host_intr5",
392 "host_intr6", "host_intr7";
396 compatible = "ti,am3356-pru";
397 reg = <0x34000 0x2000>,
400 reg-names = "iram", "control", "debug";
401 firmware-name = "am335x-pru0-fw";
405 compatible = "ti,am3356-pru";
406 reg = <0x38000 0x2000>,
409 reg-names = "iram", "control", "debug";
410 firmware-name = "am335x-pru1-fw";
413 pruss_mdio: mdio@32400 {
414 compatible = "ti,davinci_mdio";
415 reg = <0x32400 0x90>;
416 clocks = <&dpll_core_m4_ck>;
418 bus_freq = <1000000>;
419 #address-cells = <1>;
426 /* Example 2 AM43xx PRU-ICSS with PRUSS1 node */
427 #include <dt-bindings/interrupt-controller/arm-gic.h>
429 compatible = "ti,am4376-pruss1";
431 #address-cells = <1>;
435 pruss1_mem: memories@0 {
439 reg-names = "dram0", "dram1", "shrdram2";
442 pruss1_cfg: cfg@26000 {
443 compatible = "ti,pruss-cfg", "syscon";
444 #address-cells = <1>;
446 reg = <0x26000 0x2000>;
447 ranges = <0x00 0x26000 0x2000>;
450 #address-cells = <1>;
453 pruss1_iepclk_mux: iepclk-mux@30 {
456 clocks = <&sysclk_div>, /* icss_iep */
457 <&pruss_ocp_gclk>; /* icss_ocp */
462 pruss1_mii_rt: mii-rt@32000 {
463 compatible = "ti,pruss-mii", "syscon";
464 reg = <0x32000 0x58>;
467 pruss1_intc: interrupt-controller@20000 {
468 compatible = "ti,pruss-intc";
469 reg = <0x20000 0x2000>;
470 interrupt-controller;
471 #interrupt-cells = <3>;
472 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
479 interrupt-names = "host_intr0", "host_intr1",
480 "host_intr2", "host_intr3",
482 "host_intr6", "host_intr7";
483 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
487 compatible = "ti,am4376-pru";
488 reg = <0x34000 0x3000>,
491 reg-names = "iram", "control", "debug";
492 firmware-name = "am437x-pru1_0-fw";
496 compatible = "ti,am4376-pru";
497 reg = <0x38000 0x3000>,
500 reg-names = "iram", "control", "debug";
501 firmware-name = "am437x-pru1_1-fw";
504 pruss1_mdio: mdio@32400 {
505 compatible = "ti,davinci_mdio";
506 reg = <0x32400 0x90>;
507 clocks = <&dpll_core_m4_ck>;
509 bus_freq = <1000000>;
510 #address-cells = <1>;