1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: GENI Serial Engine QUP Wrapper Controller
10 - Mukesh Savaliya <msavaliy@codeaurora.org>
11 - Akash Asthana <akashast@codeaurora.org>
14 Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
15 is a programmable module for supporting a wide range of serial interfaces
16 like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
17 Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
18 Wrapper controller is modeled as a node with zero or more child nodes each
19 representing a serial engine.
27 description: QUP wrapper common register address and length.
37 - description: Master AHB Clock
38 - description: Slave AHB Clock
69 description: Common properties for GENI Serial Engine based I2C, SPI and
74 description: GENI Serial Engine register address and length.
81 description: Serial engine core clock needed by the device.
102 description: GENI serial engine based SPI controller. SPI in master mode
103 supports up to 50MHz, up to four chip selects, programmable
104 data path from 4 bits to 32 bits and numerous protocol
106 $ref: /spi/spi-controller.yaml#
130 description: GENI serial engine based I2C controller.
131 $ref: /schemas/i2c/i2c-controller.yaml#
148 description: Desired I2C bus clock frequency in Hz.
159 description: GENI Serial Engine based UART Controller.
160 $ref: /schemas/serial.yaml#
166 - qcom,geni-debug-uart
171 - description: UART core irq
172 - description: Wakeup irq (RX GPIO)
178 additionalProperties: false
182 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
183 #include <dt-bindings/interrupt-controller/arm-gic.h>
186 #address-cells = <2>;
190 compatible = "qcom,geni-se-qup";
191 reg = <0 0x008c0000 0 0x6000>;
192 clock-names = "m-ahb", "s-ahb";
193 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
194 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
195 #address-cells = <2>;
200 compatible = "qcom,geni-i2c";
201 reg = <0 0xa94000 0 0x4000>;
202 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
205 pinctrl-names = "default", "sleep";
206 pinctrl-0 = <&qup_1_i2c_5_active>;
207 pinctrl-1 = <&qup_1_i2c_5_sleep>;
208 #address-cells = <1>;
212 uart0: serial@a88000 {
213 compatible = "qcom,geni-uart";
214 reg = <0 0xa88000 0 0x7000>;
215 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
218 pinctrl-names = "default", "sleep";
219 pinctrl-0 = <&qup_1_uart_3_active>;
220 pinctrl-1 = <&qup_1_uart_3_sleep>;