Documentation/devicetree/bindings/serial/renesas,scif.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: "http://devicetree.org/schemas/serial/renesas,scif.yaml#"
   5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   6
   7 title: Renesas Serial Communication Interface with FIFO (SCIF)
   8
   9 maintainers:
  10   - Geert Uytterhoeven <geert+renesas@glider.be>
  11
  12 allOf:
  13   - $ref: serial.yaml#
  14
  15 properties:
  16   compatible:
  17     oneOf:
  18       - items:
  19           - enum:
  20               - renesas,scif-r7s72100     # RZ/A1H
  21           - const: renesas,scif           # generic SCIF compatible UART
  22
  23       - items:
  24           - enum:
  25               - renesas,scif-r7s9210      # RZ/A2
  26
  27       - items:
  28           - enum:
  29               - renesas,scif-r8a7778      # R-Car M1
  30               - renesas,scif-r8a7779      # R-Car H1
  31           - const: renesas,rcar-gen1-scif # R-Car Gen1
  32           - const: renesas,scif           # generic SCIF compatible UART
  33
  34       - items:
  35           - enum:
  36               - renesas,scif-r8a7742      # RZ/G1H
  37               - renesas,scif-r8a7743      # RZ/G1M
  38               - renesas,scif-r8a7744      # RZ/G1N
  39               - renesas,scif-r8a7745      # RZ/G1E
  40               - renesas,scif-r8a77470     # RZ/G1C
  41               - renesas,scif-r8a7790      # R-Car H2
  42               - renesas,scif-r8a7791      # R-Car M2-W
  43               - renesas,scif-r8a7792      # R-Car V2H
  44               - renesas,scif-r8a7793      # R-Car M2-N
  45               - renesas,scif-r8a7794      # R-Car E2
  46           - const: renesas,rcar-gen2-scif # R-Car Gen2 and RZ/G1
  47           - const: renesas,scif           # generic SCIF compatible UART
  48
  49       - items:
  50           - enum:
  51               - renesas,scif-r8a774a1     # RZ/G2M
  52               - renesas,scif-r8a774b1     # RZ/G2N
  53               - renesas,scif-r8a774c0     # RZ/G2E
  54               - renesas,scif-r8a7795      # R-Car H3
  55               - renesas,scif-r8a7796      # R-Car M3-W
  56               - renesas,scif-r8a77961     # R-Car M3-W+
  57               - renesas,scif-r8a77965     # R-Car M3-N
  58               - renesas,scif-r8a77970     # R-Car V3M
  59               - renesas,scif-r8a77980     # R-Car V3H
  60               - renesas,scif-r8a77990     # R-Car E3
  61               - renesas,scif-r8a77995     # R-Car D3
  62           - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2
  63           - const: renesas,scif           # generic SCIF compatible UART
  64
  65   reg:
  66     maxItems: 1
  67
  68   interrupts:
  69     oneOf:
  70       - items:
  71           - description: A combined interrupt
  72       - items:
  73           - description: Error interrupt
  74           - description: Receive buffer full interrupt
  75           - description: Transmit buffer empty interrupt
  76           - description: Transmit End interrupt
  77       - items:
  78           - description: Error interrupt
  79           - description: Receive buffer full interrupt
  80           - description: Transmit buffer empty interrupt
  81           - description: Break interrupt
  82           - description: Data Ready interrupt
  83           - description: Transmit End interrupt
  84
  85   interrupt-names:
  86     oneOf:
  87       - items:
  88           - const: eri
  89           - const: rxi
  90           - const: txi
  91           - const: tei
  92       - items:
  93           - const: eri
  94           - const: rxi
  95           - const: txi
  96           - const: bri
  97           - const: dri
  98           - const: tei
  99
 100   clocks:
 101     minItems: 1
 102     maxItems: 4
 103
 104   clock-names:
 105     minItems: 1
 106     maxItems: 4
 107     items:
 108       enum:
 109         - fck # UART functional clock
 110         - sck # optional external clock input
 111         - brg_int # optional internal clock source for BRG frequency divider
 112         - scif_clk # optional external clock source for BRG frequency divider
 113
 114   power-domains:
 115     maxItems: 1
 116
 117   resets:
 118     maxItems: 1
 119
 120   dmas:
 121     description:
 122       Must contain a list of pairs of references to DMA specifiers, one for
 123       transmission, and one for reception.
 124
 125   dma-names:
 126     minItems: 2
 127     maxItems: 4
 128     items:
 129       enum:
 130         - tx
 131         - rx
 132
 133 required:
 134   - compatible
 135   - reg
 136   - interrupts
 137   - clocks
 138   - clock-names
 139   - power-domains
 140
 141 if:
 142   properties:
 143     compatible:
 144       contains:
 145         enum:
 146           - renesas,rcar-gen2-scif
 147           - renesas,rcar-gen3-scif
 148 then:
 149   required:
 150     - resets
 151
 152 unevaluatedProperties: false
 153
 154 examples:
 155   - |
 156     #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
 157     #include <dt-bindings/interrupt-controller/arm-gic.h>
 158     #include <dt-bindings/power/r8a7791-sysc.h>
 159     aliases {
 160             serial0 = &scif0;
 161     };
 162
 163     scif0: serial@e6e60000 {
 164             compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
 165                          "renesas,scif";
 166             reg = <0xe6e60000 64>;
 167             interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 168             clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
 169                      <&scif_clk>;
 170             clock-names = "fck", "brg_int", "scif_clk";
 171             dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>;
 172             dma-names = "tx", "rx", "tx", "rx";
 173             power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 174             resets = <&cpg 721>;
 175     };