1 # Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
4 $id: http://devicetree.org/schemas/serial/8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART (Universal Asynchronous Receiver/Transmitter) bindings
10 - devicetree@vger.kernel.org
19 - aspeed,lpc-interrupts
21 - aspeed,sirq-polarity-sense
25 const: aspeed,ast2500-vuart
48 - required: [ clock-frequency ]
49 - required: [ clocks ]
59 - const: aspeed,ast2400-vuart
60 - const: aspeed,ast2500-vuart
61 - const: intel,xscale-uart
62 - const: mrvl,pxa-uart
63 - const: nuvoton,wpcm450-uart
64 - const: nuvoton,npcm750-uart
65 - const: nvidia,tegra20-uart
66 - const: nxp,lpc3220-uart
76 - opencores,uart16550-rtlsvn105
82 - cavium,octeon-3860-uart
83 - xlnx,xps-uart16550-2.00.b
86 - ns16550 # Deprecated, unless the FIFO really is broken
93 - const: ralink,rt2880-uart
95 - ns16550 # Deprecated, unless the FIFO really is broken
99 - mediatek,mt7622-btif
100 - mediatek,mt7623-btif
101 - const: mediatek,mtk-btif
103 - const: mrvl,mmp-uart
104 - const: intel,xscale-uart
107 - nvidia,tegra30-uart
108 - nvidia,tegra114-uart
109 - nvidia,tegra124-uart
110 - nvidia,tegra186-uart
111 - nvidia,tegra194-uart
112 - nvidia,tegra210-uart
113 - const: nvidia,tegra20-uart
121 clock-frequency: true
130 $ref: /schemas/types.yaml#/definitions/uint32
131 description: The current active speed of the UART.
135 Offset to apply to the mapbase from the start of the registers.
138 description: Quantity to shift the register offsets by.
142 The size (in bytes) of the IO accesses that should be performed on the
143 device. There are some systems that require 32-bit accesses to the
144 UART (e.g. TI davinci).
149 Set to indicate that the port is in use by the OpenFirmware RTAS and
150 should not be registered.
155 Set to indicate that the port does not implement loopback test mode.
158 $ref: /schemas/types.yaml#/definitions/uint32
159 description: The fifo size of the UART.
164 One way to enable automatic flow control support. The driver is
165 allowed to detect support for the capability even without this
170 Specify the TX FIFO low water indication for parts with programmable
175 How long to pause uart rx when input overrun is encountered.
184 aspeed,sirq-polarity-sense:
185 $ref: /schemas/types.yaml#/definitions/phandle-array
187 Phandle to aspeed,ast2500-scu compatible syscon alongside register
188 offset and bit number to identify how the SIRQ polarity should be
189 configured. One possible data source is the LPC/eSPI mode bit. Only
190 applicable to aspeed,ast2500-vuart.
194 $ref: '/schemas/types.yaml#/definitions/uint32'
196 The VUART LPC address. Only applicable to aspeed,ast2500-vuart.
198 aspeed,lpc-interrupts:
199 $ref: "/schemas/types.yaml#/definitions/uint32-array"
203 A 2-cell property describing the VUART SIRQ number and SIRQ
204 polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only
205 applicable to aspeed,ast2500-vuart.
211 unevaluatedProperties: false
216 compatible = "ns8250";
217 reg = <0x80230000 0x100>;
220 clock-frequency = <48000000>;
223 #include <dt-bindings/gpio/gpio.h>
225 compatible = "andestech,uart16550", "ns16550a";
226 reg = <0x49042000 0x400>;
228 clock-frequency = <48000000>;
229 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
230 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
231 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
232 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
233 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
234 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
237 #include <dt-bindings/clock/aspeed-clock.h>
238 #include <dt-bindings/interrupt-controller/irq.h>
240 compatible = "aspeed,ast2500-vuart";
241 reg = <0x1e787000 0x40>;
244 clocks = <&syscon ASPEED_CLK_APB>;
246 aspeed,lpc-io-reg = <0x3f8>;
247 aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;