Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 # Copyright (C) STMicroelectronics 2019.
   3 %YAML 1.2
   4 ---
   5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
   6 $schema: http://devicetree.org/meta-schemas/core.yaml#
   7
   8 title: STM32 GPIO and Pin Mux/Config controller
   9
  10 maintainers:
  11   - Alexandre TORGUE <alexandre.torgue@st.com>
  12
  13 description: |
  14   STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
  15   controller. It controls the input/output settings on the available pins and
  16   also provides ability to multiplex and configure the output of various
  17   on-chip controllers onto these pads.
  18
  19 properties:
  20   compatible:
  21     enum:
  22       - st,stm32f429-pinctrl
  23       - st,stm32f469-pinctrl
  24       - st,stm32f746-pinctrl
  25       - st,stm32f769-pinctrl
  26       - st,stm32h743-pinctrl
  27       - st,stm32mp157-pinctrl
  28       - st,stm32mp157-z-pinctrl
  29
  30   '#address-cells':
  31     const: 1
  32   '#size-cells':
  33     const: 1
  34
  35   ranges: true
  36   pins-are-numbered: true
  37   hwlocks: true
  38
  39   interrupts:
  40     maxItems: 1
  41
  42   st,syscfg:
  43     description: Should be phandle/offset/mask
  44       - Phandle to the syscon node which includes IRQ mux selection.
  45       - The offset of the IRQ mux selection register.
  46       - The field mask of IRQ mux, needed if different of 0xf.
  47     $ref: "/schemas/types.yaml#/definitions/phandle-array"
  48
  49   st,package:
  50     description:
  51       Indicates the SOC package used.
  52       More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
  53     $ref: /schemas/types.yaml#/definitions/uint32
  54     enum: [1, 2, 4, 8]
  55
  56 patternProperties:
  57   '^gpio@[0-9a-f]*$':
  58     type: object
  59     properties:
  60       gpio-controller: true
  61       '#gpio-cells':
  62         const: 2
  63
  64       reg:
  65         maxItems: 1
  66       clocks:
  67         maxItems: 1
  68       reset:
  69         minItems: 1
  70         maxItems: 1
  71       gpio-ranges:
  72         minItems: 1
  73         maxItems: 16
  74       ngpios:
  75         description:
  76           Number of available gpios in a bank.
  77         minimum: 1
  78         maximum: 16
  79
  80       st,bank-name:
  81         description:
  82           Should be a name string for this bank as specified in the datasheet.
  83         $ref: "/schemas/types.yaml#/definitions/string"
  84         enum:
  85           - GPIOA
  86           - GPIOB
  87           - GPIOC
  88           - GPIOD
  89           - GPIOE
  90           - GPIOF
  91           - GPIOG
  92           - GPIOH
  93           - GPIOI
  94           - GPIOJ
  95           - GPIOK
  96           - GPIOZ
  97
  98       st,bank-ioport:
  99         description:
 100           Should correspond to the EXTI IOport selection (EXTI line used
 101           to select GPIOs as interrupts).
 102         $ref: "/schemas/types.yaml#/definitions/uint32"
 103         minimum: 0
 104         maximum: 11
 105
 106     required:
 107       - gpio-controller
 108       - '#gpio-cells'
 109       - reg
 110       - clocks
 111       - st,bank-name
 112
 113   '-[0-9]*$':
 114     type: object
 115     patternProperties:
 116       '^pins':
 117         type: object
 118         description: |
 119           A pinctrl node should contain at least one subnode representing the
 120           pinctrl group available on the machine. Each subnode will list the
 121           pins it needs, and how they should be configured, with regard to muxer
 122           configuration, pullups, drive, output high/low and output speed.
 123         properties:
 124           pinmux:
 125             $ref: "/schemas/types.yaml#/definitions/uint32-array"
 126             description: |
 127               Integer array, represents gpio pin number and mux setting.
 128               Supported pin number and mux varies for different SoCs, and are
 129               defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
 130               These defines are calculated as: ((port * 16 + line) << 8) | function
 131               With:
 132               - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
 133               - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
 134               - function: The function number, can be:
 135               * 0 : GPIO
 136               * 1 : Alternate Function 0
 137               * 2 : Alternate Function 1
 138               * 3 : Alternate Function 2
 139               * ...
 140               * 16 : Alternate Function 15
 141               * 17 : Analog
 142               To simplify the usage, macro is available to generate "pinmux" field.
 143               This macro is available here:
 144                 - include/dt-bindings/pinctrl/stm32-pinfunc.h
 145               Some examples of using macro:
 146                /* GPIO A9 set as alernate function 2 */
 147                ... {
 148                           pinmux = <STM32_PINMUX('A', 9, AF2)>;
 149                };
 150                /* GPIO A9 set as GPIO  */
 151                ... {
 152                           pinmux = <STM32_PINMUX('A', 9, GPIO)>;
 153                };
 154                /* GPIO A9 set as analog */
 155                ... {
 156                           pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
 157                };
 158
 159           bias-disable:
 160             type: boolean
 161           bias-pull-down:
 162             type: boolean
 163           bias-pull-up:
 164             type: boolean
 165           drive-push-pull:
 166             type: boolean
 167           drive-open-drain:
 168             type: boolean
 169           output-low:
 170             type: boolean
 171           output-high:
 172             type: boolean
 173           slew-rate:
 174             description: |
 175               0: Low speed
 176               1: Medium speed
 177               2: Fast speed
 178               3: High speed
 179             $ref: /schemas/types.yaml#/definitions/uint32
 180             enum: [0, 1, 2, 3]
 181
 182         required:
 183           - pinmux
 184
 185 required:
 186   - compatible
 187   - '#address-cells'
 188   - '#size-cells'
 189   - ranges
 190   - pins-are-numbered
 191
 192 additionalProperties: false
 193
 194 examples:
 195   - |
 196     #include <dt-bindings/pinctrl/stm32-pinfunc.h>
 197     #include <dt-bindings/mfd/stm32f4-rcc.h>
 198     //Example 1
 199       pinctrl@40020000 {
 200               #address-cells = <1>;
 201               #size-cells = <1>;
 202               compatible = "st,stm32f429-pinctrl";
 203               ranges = <0 0x40020000 0x3000>;
 204               pins-are-numbered;
 205
 206               gpioa: gpio@0 {
 207                       gpio-controller;
 208                       #gpio-cells = <2>;
 209                       reg = <0x0 0x400>;
 210                       resets = <&reset_ahb1 0>;
 211                       clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
 212                       st,bank-name = "GPIOA";
 213               };
 214        };
 215
 216     //Example 2 (using gpio-ranges)
 217       pinctrl@50020000 {
 218               #address-cells = <1>;
 219               #size-cells = <1>;
 220               compatible = "st,stm32f429-pinctrl";
 221               ranges = <0 0x50020000 0x3000>;
 222               pins-are-numbered;
 223
 224               gpiob: gpio@1000 {
 225                       gpio-controller;
 226                       #gpio-cells = <2>;
 227                       reg = <0x1000 0x400>;
 228                       resets = <&reset_ahb1 0>;
 229                       clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
 230                       st,bank-name = "GPIOB";
 231                       gpio-ranges = <&pinctrl 0 0 16>;
 232               };
 233
 234               gpioc: gpio@2000 {
 235                       gpio-controller;
 236                       #gpio-cells = <2>;
 237                       reg = <0x2000 0x400>;
 238                       resets = <&reset_ahb1 0>;
 239                       clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
 240                       st,bank-name = "GPIOC";
 241                       ngpios = <5>;
 242                       gpio-ranges = <&pinctrl 0 16 3>,
 243                                     <&pinctrl 14 30 2>;
 244               };
 245       };
 246
 247     //Example 3 pin groups
 248       pinctrl {
 249         usart1_pins_a: usart1-0 {
 250                 pins1 {
 251                         pinmux = <STM32_PINMUX('A', 9, AF7)>;
 252                         bias-disable;
 253                         drive-push-pull;
 254                         slew-rate = <0>;
 255                 };
 256                 pins2 {
 257                         pinmux = <STM32_PINMUX('A', 10, AF7)>;
 258                         bias-disable;
 259                 };
 260         };
 261     };
 262
 263     usart1 {
 264                 pinctrl-0 = <&usart1_pins_a>;
 265                 pinctrl-names = "default";
 266     };
 267
 268 ...