1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright (C) STMicroelectronics 2019.
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: STM32 GPIO and Pin Mux/Config controller
11 - Alexandre TORGUE <alexandre.torgue@st.com>
14 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
15 controller. It controls the input/output settings on the available pins and
16 also provides ability to multiplex and configure the output of various
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
26 - st,stm32h743-pinctrl
27 - st,stm32mp135-pinctrl
28 - st,stm32mp157-pinctrl
29 - st,stm32mp157-z-pinctrl
37 pins-are-numbered: true
44 description: Should be phandle/offset/mask
45 - Phandle to the syscon node which includes IRQ mux selection.
46 - The offset of the IRQ mux selection register.
47 - The field mask of IRQ mux, needed if different of 0xf.
48 $ref: "/schemas/types.yaml#/definitions/phandle-array"
52 Indicates the SOC package used.
53 More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
54 $ref: /schemas/types.yaml#/definitions/uint32
77 Number of available gpios in a bank.
83 Should be a name string for this bank as specified in the datasheet.
84 $ref: "/schemas/types.yaml#/definitions/string"
101 Should correspond to the EXTI IOport selection (EXTI line used
102 to select GPIOs as interrupts).
103 $ref: "/schemas/types.yaml#/definitions/uint32"
120 A pinctrl node should contain at least one subnode representing the
121 pinctrl group available on the machine. Each subnode will list the
122 pins it needs, and how they should be configured, with regard to muxer
123 configuration, pullups, drive, output high/low and output speed.
126 $ref: "/schemas/types.yaml#/definitions/uint32-array"
128 Integer array, represents gpio pin number and mux setting.
129 Supported pin number and mux varies for different SoCs, and are
130 defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
131 These defines are calculated as: ((port * 16 + line) << 8) | function
133 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
134 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
135 - function: The function number, can be:
137 * 1 : Alternate Function 0
138 * 2 : Alternate Function 1
139 * 3 : Alternate Function 2
141 * 16 : Alternate Function 15
143 To simplify the usage, macro is available to generate "pinmux" field.
144 This macro is available here:
145 - include/dt-bindings/pinctrl/stm32-pinfunc.h
146 Some examples of using macro:
147 /* GPIO A9 set as alernate function 2 */
149 pinmux = <STM32_PINMUX('A', 9, AF2)>;
151 /* GPIO A9 set as GPIO */
153 pinmux = <STM32_PINMUX('A', 9, GPIO)>;
155 /* GPIO A9 set as analog */
157 pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
180 $ref: /schemas/types.yaml#/definitions/uint32
193 additionalProperties: false
197 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
198 #include <dt-bindings/mfd/stm32f4-rcc.h>
201 #address-cells = <1>;
203 compatible = "st,stm32f429-pinctrl";
204 ranges = <0 0x40020000 0x3000>;
211 resets = <&reset_ahb1 0>;
212 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
213 st,bank-name = "GPIOA";
217 //Example 2 (using gpio-ranges)
219 #address-cells = <1>;
221 compatible = "st,stm32f429-pinctrl";
222 ranges = <0 0x50020000 0x3000>;
228 reg = <0x1000 0x400>;
229 resets = <&reset_ahb1 0>;
230 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
231 st,bank-name = "GPIOB";
232 gpio-ranges = <&pinctrl 0 0 16>;
238 reg = <0x2000 0x400>;
239 resets = <&reset_ahb1 0>;
240 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
241 st,bank-name = "GPIOC";
243 gpio-ranges = <&pinctrl 0 16 3>,
248 //Example 3 pin groups
250 usart1_pins_a: usart1-0 {
252 pinmux = <STM32_PINMUX('A', 9, AF7)>;
258 pinmux = <STM32_PINMUX('A', 10, AF7)>;
265 pinctrl-0 = <&usart1_pins_a>;
266 pinctrl-names = "default";