1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI J721E WIZ (SERDES Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
25 description: clock-specifier to represent input to the WIZ
55 assigned-clock-parents:
66 GPIO to signal Type-C cable orientation for lane swap.
67 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
68 achieve the funtionality of an external type-C plug flip mux.
70 typec-dir-debounce-ms:
75 Number of milliseconds to wait before sampling typec-dir-gpio.
76 If not specified, the default debounce of 100ms will be used.
77 Type-C spec states minimum CC pin debounce of 100 ms and maximum
78 of 200 ms. However, some solutions might need more than 200 ms.
83 WIZ node should have subnode for refclk_dig to select the reference
84 clock source for the reference clock used in the PHY and PMA digital
90 description: Phandle to two (Torrent) or four (Sierra) clock nodes representing
91 the inputs to refclk_dig
99 assigned-clock-parents:
106 - assigned-clock-parents
112 WIZ node should have subnodes for each of the PLLs present in
117 description: Phandle to clock nodes representing the two inputs to PLL.
125 assigned-clock-parents:
132 - assigned-clock-parents
134 "^cmn-refclk1?-dig-div$":
137 WIZ node should have subnodes for each of the PMA common refclock
138 provided by the SERDES.
142 description: Phandle to the clock node representing the input to the
152 "^serdes@[0-9a-f]+$":
155 WIZ node should have '1' subnode for the SERDES. It could be either
156 Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
157 bindings specified in
158 Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
159 Torrent SERDES should follow the bindings specified in
160 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
173 additionalProperties: false
177 #include <dt-bindings/soc/ti,sci_pm_domain.h>
180 compatible = "ti,j721e-wiz-16g";
181 #address-cells = <1>;
183 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
184 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
185 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
186 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
187 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
190 ranges = <0x5000000 0x5000000 0x10000>;
193 clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
195 assigned-clocks = <&wiz1_pll0_refclk>;
196 assigned-clock-parents = <&k3_clks 293 13>;
200 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
202 assigned-clocks = <&wiz1_pll1_refclk>;
203 assigned-clock-parents = <&k3_clks 293 0>;
207 clocks = <&wiz1_refclk_dig>;
211 cmn-refclk1-dig-div {
212 clocks = <&wiz1_pll1_refclk>;
217 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
218 <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
220 assigned-clocks = <&wiz0_refclk_dig>;
221 assigned-clock-parents = <&k3_clks 292 11>;
225 compatible = "ti,sierra-phy-t0";
226 reg-names = "serdes";
227 reg = <0x5000000 0x10000>;
228 #address-cells = <1>;
230 resets = <&serdes_wiz0 0>;
231 reset-names = "sierra_reset";
232 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
233 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";