Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings
   8
   9 maintainers:
  10   - Heiko Stuebner <heiko@sntech.de>
  11
  12 description: |
  13   The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP wich
  14   connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.
  15
  16 properties:
  17   compatible:
  18     enum:
  19       - rockchip,px30-csi-dphy
  20       - rockchip,rk1808-csi-dphy
  21       - rockchip,rk3326-csi-dphy
  22       - rockchip,rk3368-csi-dphy
  23
  24   reg:
  25     maxItems: 1
  26
  27   clocks:
  28     maxItems: 1
  29
  30   clock-names:
  31     const: pclk
  32
  33   '#phy-cells':
  34     const: 0
  35
  36   power-domains:
  37     description: Video in/out power domain.
  38     maxItems: 1
  39
  40   resets:
  41     items:
  42       - description: exclusive PHY reset line
  43
  44   reset-names:
  45     items:
  46       - const: apb
  47
  48   rockchip,grf:
  49     $ref: /schemas/types.yaml#/definitions/phandle
  50     description:
  51       Some additional phy settings are access through GRF regs.
  52
  53 required:
  54   - compatible
  55   - reg
  56   - clocks
  57   - clock-names
  58   - '#phy-cells'
  59   - power-domains
  60   - resets
  61   - reset-names
  62   - rockchip,grf
  63
  64 additionalProperties: false
  65
  66 examples:
  67   - |
  68
  69     csi_dphy: phy@ff2f0000 {
  70         compatible = "rockchip,px30-csi-dphy";
  71         reg = <0xff2f0000 0x4000>;
  72         clocks = <&cru 1>;
  73         clock-names = "pclk";
  74         #phy-cells = <0>;
  75         power-domains = <&power 1>;
  76         resets = <&cru 1>;
  77         reset-names = "apb";
  78         rockchip,grf = <&grf>;
  79     };