Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2
   3 %YAML 1.2
   4 ---
   5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
   6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   7
   8 title: Qualcomm QMP USB3 DP PHY controller
   9
  10 maintainers:
  11   - Manu Gautam <mgautam@codeaurora.org>
  12
  13 properties:
  14   compatible:
  15     enum:
  16       - qcom,sc7180-qmp-usb3-dp-phy
  17       - qcom,sdm845-qmp-usb3-dp-phy
  18       - qcom,sm8250-qmp-usb3-dp-phy
  19   reg:
  20     items:
  21       - description: Address and length of PHY's USB serdes block.
  22       - description: Address and length of the DP_COM control block.
  23       - description: Address and length of PHY's DP serdes block.
  24
  25   reg-names:
  26     items:
  27       - const: usb
  28       - const: dp_com
  29       - const: dp
  30
  31   "#clock-cells":
  32     enum: [ 1, 2 ]
  33
  34   "#address-cells":
  35     enum: [ 1, 2 ]
  36
  37   "#size-cells":
  38     enum: [ 1, 2 ]
  39
  40   ranges: true
  41
  42   clocks:
  43     items:
  44       - description: Phy aux clock.
  45       - description: Phy config clock.
  46       - description: 19.2 MHz ref clk.
  47       - description: Phy common block aux clock.
  48
  49   clock-names:
  50     items:
  51       - const: aux
  52       - const: cfg_ahb
  53       - const: ref
  54       - const: com_aux
  55
  56   resets:
  57     items:
  58       - description: reset of phy block.
  59       - description: phy common block reset.
  60
  61   reset-names:
  62     items:
  63       - const: phy
  64       - const: common
  65
  66   vdda-phy-supply:
  67     description:
  68       Phandle to a regulator supply to PHY core block.
  69
  70   vdda-pll-supply:
  71     description:
  72       Phandle to 1.8V regulator supply to PHY refclk pll block.
  73
  74   vddp-ref-clk-supply:
  75     description:
  76       Phandle to a regulator supply to any specific refclk pll block.
  77
  78 #Required nodes:
  79 patternProperties:
  80   "^usb3-phy@[0-9a-f]+$":
  81     type: object
  82     description:
  83       The USB3 PHY.
  84
  85     properties:
  86       reg:
  87         items:
  88           - description: Address and length of TX.
  89           - description: Address and length of RX.
  90           - description: Address and length of PCS.
  91           - description: Address and length of TX2.
  92           - description: Address and length of RX2.
  93           - description: Address and length of pcs_misc.
  94
  95       clocks:
  96         items:
  97           - description: pipe clock
  98
  99       clock-names:
 100         items:
 101           - const: pipe0
 102
 103       clock-output-names:
 104         items:
 105           - const: usb3_phy_pipe_clk_src
 106
 107       '#clock-cells':
 108         const: 0
 109
 110       '#phy-cells':
 111         const: 0
 112
 113     required:
 114       - reg
 115       - clocks
 116       - clock-names
 117       - '#clock-cells'
 118       - '#phy-cells'
 119
 120   "^dp-phy@[0-9a-f]+$":
 121     type: object
 122     description:
 123       The DP PHY.
 124
 125     properties:
 126       reg:
 127         items:
 128           - description: Address and length of TX.
 129           - description: Address and length of RX.
 130           - description: Address and length of PCS.
 131           - description: Address and length of TX2.
 132           - description: Address and length of RX2.
 133
 134       '#clock-cells':
 135         const: 1
 136
 137       '#phy-cells':
 138         const: 0
 139
 140     required:
 141       - reg
 142       - '#clock-cells'
 143       - '#phy-cells'
 144
 145 required:
 146   - compatible
 147   - reg
 148   - "#clock-cells"
 149   - "#address-cells"
 150   - "#size-cells"
 151   - ranges
 152   - clocks
 153   - clock-names
 154   - resets
 155   - reset-names
 156   - vdda-phy-supply
 157   - vdda-pll-supply
 158
 159 additionalProperties: false
 160
 161 examples:
 162   - |
 163     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 164     usb_1_qmpphy: phy-wrapper@88e9000 {
 165         compatible = "qcom,sdm845-qmp-usb3-dp-phy";
 166         reg = <0x088e9000 0x18c>,
 167               <0x088e8000 0x10>,
 168               <0x088ea000 0x40>;
 169         reg-names = "usb", "dp_com", "dp";
 170         #clock-cells = <1>;
 171         #address-cells = <1>;
 172         #size-cells = <1>;
 173         ranges = <0x0 0x088e9000 0x2000>;
 174
 175         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
 176                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 177                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
 178                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
 179         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
 180
 181         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
 182                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
 183         reset-names = "phy", "common";
 184
 185         vdda-phy-supply = <&vdda_usb2_ss_1p2>;
 186         vdda-pll-supply = <&vdda_usb2_ss_core>;
 187
 188         usb3-phy@200 {
 189             reg = <0x200 0x128>,
 190                   <0x400 0x200>,
 191                   <0xc00 0x218>,
 192                   <0x600 0x128>,
 193                   <0x800 0x200>,
 194                   <0xa00 0x100>;
 195             #clock-cells = <0>;
 196             #phy-cells = <0>;
 197             clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
 198             clock-names = "pipe0";
 199             clock-output-names = "usb3_phy_pipe_clk_src";
 200         };
 201
 202         dp-phy@88ea200 {
 203             reg = <0xa200 0x200>,
 204                   <0xa400 0x200>,
 205                   <0xaa00 0x200>,
 206                   <0xa600 0x200>,
 207                   <0xa800 0x200>;
 208             #clock-cells = <1>;
 209             #phy-cells = <0>;
 210         };
 211     };