Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: CPM Host Controller device tree for Xilinx Versal SoCs
   8
   9 maintainers:
  10   - Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
  11
  12 allOf:
  13   - $ref: /schemas/pci/pci-bus.yaml#
  14
  15 properties:
  16   compatible:
  17     const: xlnx,versal-cpm-host-1.00
  18
  19   reg:
  20     items:
  21       - description: Configuration space region and bridge registers.
  22       - description: CPM system level control and status registers.
  23
  24   reg-names:
  25     items:
  26       - const: cfg
  27       - const: cpm_slcr
  28
  29   interrupts:
  30     maxItems: 1
  31
  32   msi-map:
  33     description:
  34       Maps a Requester ID to an MSI controller and associated MSI sideband data.
  35
  36   ranges:
  37     maxItems: 2
  38
  39   "#interrupt-cells":
  40     const: 1
  41
  42   interrupt-controller:
  43     description: Interrupt controller node for handling legacy PCI interrupts.
  44     type: object
  45     properties:
  46       "#address-cells":
  47         const: 0
  48       "#interrupt-cells":
  49         const: 1
  50       "interrupt-controller": true
  51     additionalProperties: false
  52
  53 required:
  54   - reg
  55   - reg-names
  56   - "#interrupt-cells"
  57   - interrupts
  58   - interrupt-parent
  59   - interrupt-map
  60   - interrupt-map-mask
  61   - bus-range
  62   - msi-map
  63   - interrupt-controller
  64
  65 unevaluatedProperties: false
  66
  67 examples:
  68   - |
  69
  70     versal {
  71                #address-cells = <2>;
  72                #size-cells = <2>;
  73                cpm_pcie: pcie@fca10000 {
  74                        compatible = "xlnx,versal-cpm-host-1.00";
  75                        device_type = "pci";
  76                        #address-cells = <3>;
  77                        #interrupt-cells = <1>;
  78                        #size-cells = <2>;
  79                        interrupts = <0 72 4>;
  80                        interrupt-parent = <&gic>;
  81                        interrupt-map-mask = <0 0 0 7>;
  82                        interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
  83                                        <0 0 0 2 &pcie_intc_0 1>,
  84                                        <0 0 0 3 &pcie_intc_0 2>,
  85                                        <0 0 0 4 &pcie_intc_0 3>;
  86                        bus-range = <0x00 0xff>;
  87                        ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
  88                                 <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
  89                        msi-map = <0x0 &its_gic 0x0 0x10000>;
  90                        reg = <0x6 0x00000000 0x0 0x10000000>,
  91                              <0x0 0xfca10000 0x0 0x1000>;
  92                        reg-names = "cfg", "cpm_slcr";
  93                        pcie_intc_0: interrupt-controller {
  94                                #address-cells = <0>;
  95                                #interrupt-cells = <1>;
  96                                interrupt-controller;
  97                        };
  98                };
  99     };