1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI J721E PCI EP (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: "cdns-pcie-ep.yaml#"
32 description: Phandle to the SYSCON entry required for configuring PCIe mode
34 $ref: /schemas/types.yaml#/definitions/phandle
41 description: clock-specifier to represent input to the PCIe
48 description: Indicates that the PCIe IP block can ensure the coherency
60 - cdns,max-outbound-regions
66 unevaluatedProperties: false
70 #include <dt-bindings/soc/ti,sci_pm_domain.h>
76 pcie0_ep: pcie-ep@d000000 {
77 compatible = "ti,j721e-pcie-ep";
78 reg = <0x00 0x02900000 0x00 0x1000>,
79 <0x00 0x02907000 0x00 0x400>,
80 <0x00 0x0d000000 0x00 0x00800000>,
81 <0x00 0x10000000 0x00 0x08000000>;
82 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
83 ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
86 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
87 clocks = <&k3_clks 239 1>;
89 cdns,max-outbound-regions = <16>;
90 max-functions = /bits/ 8 <6>;
92 phys = <&serdes0_pcie_link>;
93 phy-names = "pcie-phy";