1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare PCIe interface
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
14 Synopsys DesignWare PCIe host controller
17 - $ref: /schemas/pci/pci-bus.yaml#
27 It should contain Data Bus Interface (dbi) and config registers for all
29 For designware core version >= 4.80, it may contain ATU address space.
37 enum: [ dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link,
38 ulreg, smu, mpu, apb, phy ]
42 number of lanes to use (this property should be specified unless
43 the link is brought already up in firmware)
47 description: GPIO pin number of PERST# signal
52 description: GPIO controlled connection to PERST# signal
61 snps,enable-cdm-check:
64 This is a boolean property and if present enables
65 automatic checking of CDM (Configuration Dependent Module) registers
66 for data corruption. CDM registers include standard PCIe configuration
67 space registers, Port Logic registers, DMA and iATU (internal Address
68 Translation Unit) registers.
72 number of view ports configured in hardware. If a platform
73 does not specify it, the driver autodetects it.
76 unevaluatedProperties: false
90 compatible = "snps,dw-pcie";
91 reg = <0xdfc00000 0x0001000>, /* IP registers */
92 <0xd0000000 0x0002000>; /* Configuration space */
93 reg-names = "dbi", "config";
96 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
97 <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
98 interrupts = <25>, <24>;
99 #interrupt-cells = <1>;