Documentation/devicetree/bindings/pci/rcar-pci-host.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 # Copyright (C) 2020 Renesas Electronics Corp.
   3 %YAML 1.2
   4 ---
   5 $id: http://devicetree.org/schemas/pci/rcar-pci-host.yaml#
   6 $schema: http://devicetree.org/meta-schemas/core.yaml#
   7
   8 title: Renesas R-Car PCIe Host
   9
  10 maintainers:
  11   - Marek Vasut <marek.vasut+renesas@gmail.com>
  12   - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  13
  14 allOf:
  15   - $ref: pci-bus.yaml#
  16
  17 properties:
  18   compatible:
  19     oneOf:
  20       - items:
  21           - enum:
  22               - renesas,pcie-r8a7742      # RZ/G1H
  23               - renesas,pcie-r8a7743      # RZ/G1M
  24               - renesas,pcie-r8a7744      # RZ/G1N
  25               - renesas,pcie-r8a7790      # R-Car H2
  26               - renesas,pcie-r8a7791      # R-Car M2-W
  27               - renesas,pcie-r8a7793      # R-Car M2-N
  28           - const: renesas,pcie-rcar-gen2 # R-Car Gen2 and RZ/G1
  29       - items:
  30           - enum:
  31               - renesas,pcie-r8a774a1     # RZ/G2M
  32               - renesas,pcie-r8a774b1     # RZ/G2N
  33               - renesas,pcie-r8a774c0     # RZ/G2E
  34               - renesas,pcie-r8a7795      # R-Car H3
  35               - renesas,pcie-r8a7796      # R-Car M3-W
  36               - renesas,pcie-r8a77961     # R-Car M3-W+
  37               - renesas,pcie-r8a77965     # R-Car M3-N
  38               - renesas,pcie-r8a77980     # R-Car V3H
  39               - renesas,pcie-r8a77990     # R-Car E3
  40           - const: renesas,pcie-rcar-gen3 # R-Car Gen3 and RZ/G2
  41
  42   reg:
  43     maxItems: 1
  44
  45   interrupts:
  46     minItems: 3
  47     maxItems: 3
  48
  49   clocks:
  50     maxItems: 2
  51
  52   clock-names:
  53     items:
  54       - const: pcie
  55       - const: pcie_bus
  56
  57   power-domains:
  58     maxItems: 1
  59
  60   resets:
  61     maxItems: 1
  62
  63   phys:
  64     maxItems: 1
  65
  66   phy-names:
  67     const: pcie
  68
  69 required:
  70   - compatible
  71   - reg
  72   - interrupts
  73   - clocks
  74   - clock-names
  75   - power-domains
  76   - resets
  77
  78 unevaluatedProperties: false
  79
  80 examples:
  81   - |
  82     #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
  83     #include <dt-bindings/interrupt-controller/arm-gic.h>
  84     #include <dt-bindings/power/r8a7791-sysc.h>
  85
  86     soc {
  87         #address-cells = <2>;
  88         #size-cells = <2>;
  89
  90         pcie: pcie@fe000000 {
  91             compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
  92             reg = <0 0xfe000000 0 0x80000>;
  93              #address-cells = <3>;
  94              #size-cells = <2>;
  95              bus-range = <0x00 0xff>;
  96              device_type = "pci";
  97              ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
  98                       <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
  99                       <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
 100                       <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
 101              dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
 102                           <0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
 103              interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 104                           <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 105                           <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 106              #interrupt-cells = <1>;
 107              interrupt-map-mask = <0 0 0 0>;
 108              interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 109              clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
 110              clock-names = "pcie", "pcie_bus";
 111              power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
 112              resets = <&cpg 319>;
 113          };
 114     };