1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 PCIe host controller
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
18 - $ref: /schemas/pci/snps,dw-pcie.yaml#
31 - description: Data Bus Interface (DBI) registers.
32 - description: PCIe configuration space region.
41 - description: builtin MSI controller.
51 - description: PCIe bridge clock.
52 - description: PCIe bus clock.
53 - description: PCIe PHY clock.
54 - description: Additional required clock entry for imx6sx-pcie,
63 - const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie
69 $ref: /schemas/types.yaml#/definitions/phandle
70 description: A phandle to an fsl,imx7d-pcie-phy node. Additional
71 required properties for imx7d-pcie and imx8mq-pcie.
75 - description: The phandle pointing to the DISPLAY domain for
76 imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
78 - description: The phandle pointing to the PCIE_PHY power domains
88 description: Phandles to PCIe-related reset lines exposed by SRC
89 IP block. Additional required by imx7d-pcie and imx8mq-pcie.
98 description: Gen1 De-emphasis value (optional required).
99 $ref: /schemas/types.yaml#/definitions/uint32
102 fsl,tx-deemph-gen2-3p5db:
103 description: Gen2 (3.5db) De-emphasis value (optional required).
104 $ref: /schemas/types.yaml#/definitions/uint32
107 fsl,tx-deemph-gen2-6db:
108 description: Gen2 (6db) De-emphasis value (optional required).
109 $ref: /schemas/types.yaml#/definitions/uint32
113 description: Gen2 TX SWING FULL value (optional required).
114 $ref: /schemas/types.yaml#/definitions/uint32
118 description: TX launch amplitude swing_low value (optional required).
119 $ref: /schemas/types.yaml#/definitions/uint32
123 description: Specify PCI Gen for link capability (optional required).
124 Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
125 requirements and thus for gen2 capability a gen2 compliant clock
126 generator should be used and configured.
127 $ref: /schemas/types.yaml#/definitions/uint32
132 description: Should specify the GPIO for controlling the PCI bus device
133 reset signal. It's not polarity aware and defaults to active-low reset
134 sequence (L=reset state, H=operation state) (optional required).
136 reset-gpio-active-high:
137 description: If present then the reset sequence using the GPIO
138 specified in the "reset-gpio" property is reversed (H=reset state,
139 L=operation state) (optional required).
142 description: Should specify the regulator in charge of PCIe port power.
143 The regulator will be enabled when initializing the PCIe host and
144 disabled either as part of the init process or when shutting down
145 the host (optional required).
148 description: Should specify the regulator in charge of VPH one of
149 the three PCIe PHY powers. This regulator can be supplied by both
150 1.8v and 3.3v voltage supplies (optional required).
170 unevaluatedProperties: false
174 #include <dt-bindings/clock/imx6qdl-clock.h>
175 #include <dt-bindings/interrupt-controller/arm-gic.h>
178 compatible = "fsl,imx6q-pcie";
179 reg = <0x01ffc000 0x04000>,
180 <0x01f00000 0x80000>;
181 reg-names = "dbi", "config";
182 #address-cells = <3>;
185 bus-range = <0x00 0xff>;
186 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>,
187 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
189 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
190 interrupt-names = "msi";
191 #interrupt-cells = <1>;
192 interrupt-map-mask = <0 0 0 0x7>;
193 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
194 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
195 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
196 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
198 <&clks IMX6QDL_CLK_LVDS1_GATE>,
199 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
200 clock-names = "pcie", "pcie_bus", "pcie_phy";