1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/renesas,etheravb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Ethernet AVB
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
17 - renesas,etheravb-r8a7742 # RZ/G1H
18 - renesas,etheravb-r8a7743 # RZ/G1M
19 - renesas,etheravb-r8a7744 # RZ/G1N
20 - renesas,etheravb-r8a7745 # RZ/G1E
21 - renesas,etheravb-r8a77470 # RZ/G1C
22 - renesas,etheravb-r8a7790 # R-Car H2
23 - renesas,etheravb-r8a7791 # R-Car M2-W
24 - renesas,etheravb-r8a7792 # R-Car V2H
25 - renesas,etheravb-r8a7793 # R-Car M2-N
26 - renesas,etheravb-r8a7794 # R-Car E2
27 - const: renesas,etheravb-rcar-gen2 # R-Car Gen2 and RZ/G1
31 - renesas,etheravb-r8a774a1 # RZ/G2M
32 - renesas,etheravb-r8a774b1 # RZ/G2N
33 - renesas,etheravb-r8a774c0 # RZ/G2E
34 - renesas,etheravb-r8a774e1 # RZ/G2H
35 - renesas,etheravb-r8a7795 # R-Car H3
36 - renesas,etheravb-r8a7796 # R-Car M3-W
37 - renesas,etheravb-r8a77961 # R-Car M3-W+
38 - renesas,etheravb-r8a77965 # R-Car M3-N
39 - renesas,etheravb-r8a77970 # R-Car V3M
40 - renesas,etheravb-r8a77980 # R-Car V3H
41 - renesas,etheravb-r8a77990 # R-Car E3
42 - renesas,etheravb-r8a77995 # R-Car D3
43 - renesas,etheravb-r8a779a0 # R-Car V3U
44 - const: renesas,etheravb-rcar-gen3 # R-Car Gen3 and RZ/G2
55 - description: AVB functional clock
56 - description: Optional TXC reference clock
78 description: Number of address cells for the MDIO bus.
82 description: Number of size cells on the MDIO bus.
85 renesas,no-ether-link:
88 Specify when a board does not provide a proper AVB_LINK signal.
90 renesas,ether-link-active-low:
93 Specify when the AVB_LINK signal is active-low instead of normal
103 "^ethernet-phy@[0-9a-f]$":
105 $ref: ethernet-phy.yaml#
120 - $ref: ethernet-controller.yaml#
127 - renesas,etheravb-rcar-gen2
128 - renesas,etheravb-r8a7795
129 - renesas,etheravb-r8a7796
130 - renesas,etheravb-r8a77961
131 - renesas,etheravb-r8a77965
136 - description: MAC register block
137 - description: Stream buffer
142 - description: MAC register block
148 const: renesas,etheravb-rcar-gen2
156 rx-internal-delay-ps: false
164 pattern: '^ch[0-9]+$'
167 - rx-internal-delay-ps
174 - renesas,etheravb-r8a774a1
175 - renesas,etheravb-r8a774b1
176 - renesas,etheravb-r8a774e1
177 - renesas,etheravb-r8a7795
178 - renesas,etheravb-r8a7796
179 - renesas,etheravb-r8a77961
180 - renesas,etheravb-r8a77965
181 - renesas,etheravb-r8a77970
182 - renesas,etheravb-r8a77980
183 - renesas,etheravb-r8a779a0
186 - tx-internal-delay-ps
189 tx-internal-delay-ps: false
195 const: renesas,etheravb-r8a77995
198 rx-internal-delay-ps:
205 const: renesas,etheravb-r8a77980
208 tx-internal-delay-ps:
211 additionalProperties: false
215 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
216 #include <dt-bindings/interrupt-controller/arm-gic.h>
217 #include <dt-bindings/power/r8a7795-sysc.h>
218 #include <dt-bindings/gpio/gpio.h>
223 avb: ethernet@e6800000 {
224 compatible = "renesas,etheravb-r8a7795",
225 "renesas,etheravb-rcar-gen3";
226 reg = <0xe6800000 0x800>, <0xe6a00000 0x10000>;
227 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
252 interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6",
253 "ch7", "ch8", "ch9", "ch10", "ch11", "ch12",
254 "ch13", "ch14", "ch15", "ch16", "ch17", "ch18",
255 "ch19", "ch20", "ch21", "ch22", "ch23", "ch24";
256 clocks = <&cpg CPG_MOD 812>;
257 iommus = <&ipmmu_ds0 16>;
258 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
261 phy-handle = <&phy0>;
262 rx-internal-delay-ps = <0>;
263 tx-internal-delay-ps = <2000>;
264 #address-cells = <1>;
267 phy0: ethernet-phy@0 {
268 rxc-skew-ps = <1500>;
270 interrupt-parent = <&gpio2>;
271 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
272 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;