Documentation/devicetree/bindings/net/marvell-pp2.txt

   1 * Marvell Armada 375 Ethernet Controller (PPv2.1)
   2   Marvell Armada 7K/8K Ethernet Controller (PPv2.2)
   3   Marvell CN913X Ethernet Controller (PPv2.3)
   4
   5 Required properties:
   6
   7 - compatible: should be one of:
   8     "marvell,armada-375-pp2"
   9     "marvell,armada-7k-pp2"
  10 - reg: addresses and length of the register sets for the device.
  11   For "marvell,armada-375-pp2", must contain the following register
  12   sets:
  13         - common controller registers
  14         - LMS registers
  15         - one register area per Ethernet port
  16   For "marvell,armada-7k-pp2" used by 7K/8K and CN913X, must contain the following register
  17   sets:
  18         - packet processor registers
  19         - networking interfaces registers
  20         - CM3 address space used for TX Flow Control
  21
  22 - clocks: pointers to the reference clocks for this device, consequently:
  23         - main controller clock (for both armada-375-pp2 and armada-7k-pp2)
  24         - GOP clock (for both armada-375-pp2 and armada-7k-pp2)
  25         - MG clock (only for armada-7k-pp2)
  26         - MG Core clock (only for armada-7k-pp2)
  27         - AXI clock (only for armada-7k-pp2)
  28 - clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk",
  29   "mg_core_clk" and "axi_clk" (the 3 latter only for armada-7k-pp2).
  30
  31 The ethernet ports are represented by subnodes. At least one port is
  32 required.
  33
  34 Required properties (port):
  35
  36 - interrupts: interrupt(s) for the port
  37 - port-id: ID of the port from the MAC point of view
  38 - gop-port-id: only for marvell,armada-7k-pp2, ID of the port from the
  39   GOP (Group Of Ports) point of view. This ID is used to index the
  40   per-port registers in the second register area.
  41 - phy-mode: See ethernet.txt file in the same directory
  42
  43 Optional properties (port):
  44
  45 - marvell,loopback: port is loopback mode
  46 - phy: a phandle to a phy node defining the PHY address (as the reg
  47   property, a single integer).
  48 - interrupt-names: if more than a single interrupt for is given, must be the
  49                    name associated to the interrupts listed. Valid names are:
  50                    "hifX", with X in [0..8], and "link". The names "tx-cpu0",
  51                    "tx-cpu1", "tx-cpu2", "tx-cpu3" and "rx-shared" are supported
  52                    for backward compatibility but shouldn't be used for new
  53                    additions.
  54 - marvell,system-controller: a phandle to the system controller.
  55
  56 Example for marvell,armada-375-pp2:
  57
  58 ethernet@f0000 {
  59         compatible = "marvell,armada-375-pp2";
  60         reg = <0xf0000 0xa000>,
  61               <0xc0000 0x3060>,
  62               <0xc4000 0x100>,
  63               <0xc5000 0x100>;
  64         clocks = <&gateclk 3>, <&gateclk 19>;
  65         clock-names = "pp_clk", "gop_clk";
  66
  67         eth0: eth0@c4000 {
  68                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  69                 port-id = <0>;
  70                 phy = <&phy0>;
  71                 phy-mode = "gmii";
  72         };
  73
  74         eth1: eth1@c5000 {
  75                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
  76                 port-id = <1>;
  77                 phy = <&phy3>;
  78                 phy-mode = "gmii";
  79         };
  80 };
  81
  82 Example for marvell,armada-7k-pp2:
  83
  84 cpm_ethernet: ethernet@0 {
  85         compatible = "marvell,armada-7k-pp22";
  86         reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
  87         clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>,
  88                  <&cpm_syscon0 1 5>, <&cpm_syscon0 1 6>, <&cpm_syscon0 1 18>;
  89         clock-names = "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_clk";
  90
  91         eth0: eth0 {
  92                 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
  93                              <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
  94                              <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
  95                              <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
  96                              <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
  97                              <ICU_GRP_NSR 59 IRQ_TYPE_LEVEL_HIGH>,
  98                              <ICU_GRP_NSR 63 IRQ_TYPE_LEVEL_HIGH>,
  99                              <ICU_GRP_NSR 67 IRQ_TYPE_LEVEL_HIGH>,
 100                              <ICU_GRP_NSR 71 IRQ_TYPE_LEVEL_HIGH>,
 101                              <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
 102                 interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
 103                                   "hif5", "hif6", "hif7", "hif8", "link";
 104                 port-id = <0>;
 105                 gop-port-id = <0>;
 106         };
 107
 108         eth1: eth1 {
 109                 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
 110                              <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
 111                              <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
 112                              <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
 113                              <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
 114                              <ICU_GRP_NSR 60 IRQ_TYPE_LEVEL_HIGH>,
 115                              <ICU_GRP_NSR 64 IRQ_TYPE_LEVEL_HIGH>,
 116                              <ICU_GRP_NSR 68 IRQ_TYPE_LEVEL_HIGH>,
 117                              <ICU_GRP_NSR 72 IRQ_TYPE_LEVEL_HIGH>,
 118                              <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
 119                 interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
 120                                   "hif5", "hif6", "hif7", "hif8", "link";
 121                 port-id = <1>;
 122                 gop-port-id = <2>;
 123         };
 124
 125         eth2: eth2 {
 126                 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
 127                              <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
 128                              <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
 129                              <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
 130                              <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
 131                              <ICU_GRP_NSR 61 IRQ_TYPE_LEVEL_HIGH>,
 132                              <ICU_GRP_NSR 65 IRQ_TYPE_LEVEL_HIGH>,
 133                              <ICU_GRP_NSR 69 IRQ_TYPE_LEVEL_HIGH>,
 134                              <ICU_GRP_NSR 73 IRQ_TYPE_LEVEL_HIGH>,
 135                              <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
 136                 interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
 137                                   "hif5", "hif6", "hif7", "hif8", "link";
 138                 port-id = <2>;
 139                 gop-port-id = <3>;
 140         };
 141 };