1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/net/fsl,fec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Fast Ethernet Controller (FEC)
10 - Joakim Zhang <qiangqing.zhang@nxp.com>
13 - $ref: ethernet-controller.yaml#
28 - const: fsl,imx25-fec
33 - const: fsl,imx27-fec
38 - const: fsl,imx6q-fec
42 - const: fsl,imx6sx-fec
44 - const: fsl,imx8mq-fec
45 - const: fsl,imx6sx-fec
51 - const: fsl,imx8mq-fec
52 - const: fsl,imx6sx-fec
54 - const: fsl,imx8qm-fec
55 - const: fsl,imx6sx-fec
59 - const: fsl,imx8qm-fec
60 - const: fsl,imx6sx-fec
90 The "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing.
91 The "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock.
92 The "ptp"(option), for IEEE1588 timer clock that requires the clock.
93 The "enet_clk_ref"(option), for MAC transmit/receiver reference clock like
94 RGMII TXC clock or RMII reference clock. It depends on board design,
95 the clock is required if RGMII TXC and RMII reference clock source from
97 The "enet_out"(option), output clock for external device, like supply clock
98 for PHY. The clock is required if PHY clock source from SOC.
99 The "enet_2x_txclk"(option), for RGMII sampling clock which fixed at 250Mhz.
100 The clock is required if SoC RGMII enable clock delay.
120 local-mac-address: true
126 nvmem-cell-names: true
128 tx-internal-delay-ps:
131 rx-internal-delay-ps:
136 Regulator that powers the Ethernet PHY.
139 $ref: /schemas/types.yaml#/definitions/uint32
141 The property is valid for enet-avb IP, which supports hw multi queues.
142 Should specify the tx queue number, otherwise set tx queue number to 1.
146 $ref: /schemas/types.yaml#/definitions/uint32
148 The property is valid for enet-avb IP, which supports hw multi queues.
149 Should specify the rx queue number, otherwise set rx queue number to 1.
153 $ref: /schemas/types.yaml#/definitions/flag
155 If present, indicates that the hardware supports waking up via magic packet.
157 fsl,err006687-workaround-present:
158 $ref: /schemas/types.yaml#/definitions/flag
160 If present indicates that the system has the hardware workaround for
161 ERR006687 applied and does not need a software workaround.
164 $ref: /schemas/types.yaml#/definitions/phandle-array
167 - description: phandle to general purpose register node
168 - description: the gpr register offset for ENET stop request
169 - description: the gpr bit offset for ENET stop request
171 Register bits of stop mode control, the format is <&gpr req_gpr req_bit>.
175 unevaluatedProperties: false
177 Specifies the mdio bus in the FEC, used as a container for phy nodes.
179 # Deprecated optional properties:
180 # To avoid these, create a phy node according to ethernet-phy.yaml in the same
181 # directory, and point the FEC's "phy-handle" property to it. Then use
182 # the phy's reset binding, again described by ethernet-phy.yaml.
187 Should specify the gpio for phy reset.
190 $ref: /schemas/types.yaml#/definitions/uint32
193 Reset duration in milliseconds. Should present only if property
194 "phy-reset-gpios" is available. Missing the property will have the
195 duration be 1 millisecond. Numbers greater than 1000 are invalid
196 and 1 millisecond will be used instead.
198 phy-reset-active-high:
202 If present then the reset sequence using the GPIO specified in the
203 "phy-reset-gpios" property is reversed (H=reset state, L=operation state).
205 phy-reset-post-delay:
206 $ref: /schemas/types.yaml#/definitions/uint32
209 Post reset delay in milliseconds. If present then a delay of phy-reset-post-delay
210 milliseconds will be observed after the phy-reset-gpios has been toggled.
211 Can be omitted thus no delay is observed. Delay is in range of 1ms to 1000ms.
212 Other delays are invalid.
219 # FIXME: We had better set additionalProperties to false to avoid invalid or at
220 # least undocumented properties. However, PHY may have a deprecated option to
221 # place PHY OF properties in the MAC node, such as Micrel PHY, and we can find
222 # these boards which is based on i.MX6QDL.
223 unevaluatedProperties: false
228 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
229 reg = <0x83fec000 0x4000>;
232 phy-reset-gpios = <&gpio2 14 0>;
233 phy-supply = <®_fec_supply>;
237 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
238 reg = <0x83fed000 0x4000>;
241 phy-reset-gpios = <&gpio2 14 0>;
242 phy-supply = <®_fec_supply>;
243 phy-handle = <ðphy0>;
246 #address-cells = <1>;
249 ethphy0: ethernet-phy@0 {
250 compatible = "ethernet-phy-ieee802.3-c22";