1 * Qualcomm Atheros QCA8xxx switch family
5 - compatible: should be one of:
10 - #size-cells: must be 0
11 - #address-cells: must be 1
15 - reset-gpios: GPIO to be used to reset the whole device
19 The integrated switch subnode should be specified according to the binding
20 described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external
21 mdio-bus each subnode describing a port needs to have a valid phandle
22 referencing the internal PHY it is connected to. This is because there's no
23 N:N mapping of port and PHY id.
24 To declare the internal mdio-bus configuration, declare a mdio node in the
25 switch node and declare the phandle for the port referencing the internal
26 PHY is connected to. In this config a internal mdio-bus is registered and
27 the mdio MASTER is used as communication.
29 Don't use mixed external and internal mdio-bus configurations, as this is
30 not supported by the hardware.
32 The CPU port of this switch is always port 0.
34 A CPU port node has the following optional node:
36 - fixed-link : Fixed-link subnode describing a link to a non-MDIO
38 Documentation/devicetree/bindings/net/fixed-link.txt
41 For QCA8K the 'fixed-link' sub-node supports only the following properties:
43 - 'speed' (integer, mandatory), to indicate the link speed. Accepted
44 values are 10, 100 and 1000
45 - 'full-duplex' (boolean, optional), to indicate that full duplex is
46 used. When absent, half duplex is assumed.
50 for the external mdio-bus configuration:
74 compatible = "qca,qca8337";
78 reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
98 phy-handle = <&phy_port1>;
104 phy-handle = <&phy_port2>;
110 phy-handle = <&phy_port3>;
116 phy-handle = <&phy_port4>;
122 phy-handle = <&phy_port5>;
128 for the internal master mdio-bus configuration:
132 compatible = "qca,qca8337";
133 #address-cells = <1>;
136 reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
140 #address-cells = <1>;
157 phy-mode = "internal";
158 phy-handle = <&phy_port1>;
164 phy-mode = "internal";
165 phy-handle = <&phy_port2>;
171 phy-mode = "internal";
172 phy-handle = <&phy_port3>;
178 phy-mode = "internal";
179 phy-handle = <&phy_port4>;
185 phy-mode = "internal";
186 phy-handle = <&phy_port5>;
191 #address-cells = <1>;