1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
17 enforced even for simple controllers supporting only one chip.
19 The ECC strength and ECC step size properties define the user
20 desires in terms of correction capability of a controller. Together,
21 they request the ECC engine to correct {strength} bit errors per
24 The interpretation of these parameters is implementation-defined, so
25 not all implementations must support all possible
26 combinations. However, implementations are encouraged to further
27 specify the value(s) they support.
31 pattern: "^nand-controller(@.*)?"
47 Contains the native Ready/Busy IDs.
51 Desired ECC engine, either hardware (most of the time
52 embedded in the NAND controller) or software correction
53 (Linux will handle the calculations). soft_bch is deprecated
54 and should be replaced by soft and nand-ecc-algo.
55 $ref: /schemas/types.yaml#/definitions/string
56 enum: [none, soft, hw, hw_syndrome, hw_oob_first, on-die]
60 Desired ECC algorithm.
61 $ref: /schemas/types.yaml#/definitions/string
62 enum: [hamming, bch, rs]
66 Bus width to the NAND chip
67 $ref: /schemas/types.yaml#/definitions/uint32
72 $ref: /schemas/types.yaml#/definitions/flag
74 With this property, the OS will search the device for a Bad
75 Block Table (BBT). If not found, it will create one, reserve
76 a few blocks at the end of the device to store it and update
77 it as the device ages. Otherwise, the out-of-band area of a
78 few pages of all the blocks will be scanned at boot time to
79 find Bad Block Markers (BBM). These markers will help to
80 build a volatile BBT in RAM.
84 Maximum number of bits that can be corrected per ECC step.
85 $ref: /schemas/types.yaml#/definitions/uint32
90 Number of data bytes covered by a single ECC step.
91 $ref: /schemas/types.yaml#/definitions/uint32
95 $ref: /schemas/types.yaml#/definitions/flag
97 Whether or not the ECC strength should be maximized. The
98 maximum ECC strength is both controller and chip
99 dependent. The ECC engine has to select the ECC config
100 providing the best strength and taking the OOB area size
101 constraint into account. This is particularly useful when
102 only the in-band area is used by the upper layers, and you
103 want to make your NAND as reliable as possible.
106 $ref: /schemas/types.yaml#/definitions/flag
108 Whether or not the NAND chip is a boot medium. Drivers might
109 use this information to select ECC algorithms supported by
110 the boot ROM or similar restrictions.
113 $ref: /schemas/types.yaml#/definitions/uint32-array
115 Contains the native Ready/Busy IDs.
119 Contains one or more GPIO descriptor (the numper of descriptor
120 depends on the number of R/B pins exposed by the flash) for the
121 Ready/Busy pins. Active state refers to the NAND ready state and
122 should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
131 additionalProperties: true
136 #address-cells = <1>;
139 /* controller specific properties */
143 nand-ecc-mode = "soft";
144 nand-ecc-algo = "bch";
146 /* controller specific properties */