1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
10 - Rob Herring <robh@kernel.org>
13 Flash chips (Memory Technology Devices) are often used for solid state
14 file systems on embedded devices.
26 - cortina,gemini-flash
28 - ge,imp3a-firmware-mirror
29 - ge,imp3a-paged-flash
30 - gef,ppc9a-firmware-mirror
31 - gef,ppc9a-paged-flash
32 - gef,sbc310-firmware-mirror
33 - gef,sbc310-paged-flash
34 - gef,sbc610-firmware-mirror
35 - gef,sbc610-paged-flash
41 - intel,PC28F640P30T85
45 - xlnx,xps-mch-emc-2.00.a
49 - cypress,cy7c1019dv33-10zsxi
60 It's possible to (optionally) define multiple "reg" tuples so that
61 non-identical chips can be described in one node.
66 description: Width (in bytes) of the bank. Equal to the device width times
67 the number of interleaved chips.
68 $ref: /schemas/types.yaml#/definitions/uint32
73 Width of a single mtd chip. If omitted, assumed to be equal to 'bank-width'.
74 $ref: /schemas/types.yaml#/definitions/uint32
77 no-unaligned-direct-access:
80 Disables the default direct mapping of the flash.
82 On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause problems
83 with JFFS2 usage, as the local bus (LPB) doesn't support unaligned
84 accesses as implemented in the JFFS2 code via memcpy(). By defining
85 "no-unaligned-direct-access", the flash will not be exposed directly to
86 the MTD users (e.g. JFFS2) any more.
90 Allows specifying the mtd name for retro capability with physmap-flash
91 drivers as boot loader pass the mtd partition via the old device name
93 $ref: /schemas/types.yaml#/definitions/string
95 use-advanced-sector-protection:
98 Enables support for the advanced sector protection (Spansion: PPB -
99 Persistent Protection Bits) locking.
102 description: The chip's physical erase block size in bytes.
103 $ref: /schemas/types.yaml#/definitions/uint32
107 List of GPIO descriptors that will be used to address the MSBs address
108 lines. The order goes from LSB to MSB.
123 $ref: partitions/partition.yaml
129 # FIXME: A parent bus may define timing properties
130 additionalProperties: true
136 compatible = "cfi-flash";
137 reg = <0xff000000 0x01000000>;
141 #address-cells = <1>;
143 ranges = <0 0xff000000 0x01000000>;
151 reg = <0xf80000 0x80000>;
157 /* An example with multiple "reg" tuples */
160 compatible = "intel,PC28F640P30T85", "cfi-flash";
161 reg = <0x00000000 0x02000000>,
162 <0x02000000 0x02000000>;
165 #address-cells = <1>;
167 ranges = <0 0 0x04000000>;
170 label = "test-part1";
171 reg = <0 0x04000000>;
176 /* An example using SRAM */
178 #address-cells = <2>;
182 compatible = "mtd-ram";
183 reg = <2 0 0x00200000>;
189 /* An example using addr-gpios */
190 #include <dt-bindings/gpio/gpio.h>
193 compatible = "cfi-flash";
194 reg = <0x20000000 0x02000000>;
196 addr-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
198 #address-cells = <1>;
200 ranges = <0 0x00000000 0x02000000>,
201 <1 0x02000000 0x02000000>;
204 label = "test-part1";
205 reg = <0 0x04000000>;