1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale General-Purpose Media Interface (GPMI) binding
10 - Han Xu <han.xu@nxp.com>
13 - $ref: "nand-controller.yaml"
16 The GPMI nand controller provides an interface to control the NAND
17 flash chips. The device tree may optionally contain sub-nodes
18 describing partitions of the address space. See partition.txt for
27 - fsl,imx6sx-gpmi-nand
32 - description: Address and length of gpmi block.
33 - description: Address and length of bch block.
56 - description: SoC gpmi io clock
57 - description: SoC gpmi apb clock
58 - description: SoC gpmi bch clock
59 - description: SoC gpmi bch apb clock
60 - description: SoC per1 bch clock
75 Protect this NAND flash with the minimum ECC strength required.
76 The required ECC strength is automatically discoverable for some
77 flash (e.g., according to the ONFI standard). However, note that
78 if this strength is not discoverable or this property is not enabled,
79 the software may chooses an implementation-defined ECC scheme.
81 fsl,no-blockmark-swap:
84 Don't swap the bad block marker from the OOB area with the byte in
85 the data area but rely on the flash based BBT for identifying bad blocks.
86 NOTE: this is only valid in conjunction with 'nand-on-flash-bbt'.
87 WARNING: on i.MX28 blockmark swapping cannot be disabled for the BootROM
88 in the FCB. Thus, partitions written from Linux with this feature turned
89 on may not be accessible by the BootROM code.
102 unevaluatedProperties: false
106 nand-controller@8000c000 {
107 #address-cells = <1>;
109 compatible = "fsl,imx28-gpmi-nand";
110 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
111 reg-names = "gpmi-nand", "bch";
113 interrupt-names = "bch";
115 clock-names = "gpmi_io";
116 dmas = <&dma_apbh 4>;