1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/mtd/brcm,brcmnand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
14 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
15 flash chips. It has a memory-mapped register interface for both control
16 registers and for its data input/output buffer. On some SoCs, this controller
17 is paired with a custom DMA engine (inventively named "Flash DMA") which
18 supports basic PROGRAM and READ functions, among other features.
20 This controller was originally designed for STB SoCs (BCM7xxx) but is now
21 available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and
22 iProc/Cygnus. Its history includes several similar (but not fully register
25 -- Additional SoC-specific NAND controller properties --
27 The NAND controller is integrated differently on the variety of SoCs on which
28 it is found. Part of this integration involves providing status and enable
29 bits with which to control the 8 exposed NAND interrupts, as well as hardware
30 for configuring the endianness of the data bus. On some SoCs, these features
31 are handled via standard, modular components (e.g., their interrupts look like
32 a normal IRQ chip), but on others, they are controlled in unique and
33 interesting ways, sometimes with registers that lump multiple NAND-related
34 functions together. The former case can be described simply by the standard
35 interrupts properties in the main controller node. But for the latter
36 exceptional cases, we define additional 'compatible' properties and associated
37 register resources within the NAND controller node above.
55 - const: brcm,brcmnand
56 - description: BCM63138 SoC-specific NAND controller
58 - const: brcm,nand-bcm63138
62 - const: brcm,brcmnand
63 - description: iProc SoC-specific NAND controller
65 - const: brcm,nand-iproc
66 - const: brcm,brcmnand-v6.1
67 - const: brcm,brcmnand
68 - description: BCM63168 SoC-specific NAND controller
70 - const: brcm,nand-bcm63168
71 - const: brcm,nand-bcm6368
72 - const: brcm,brcmnand-v4.0
73 - const: brcm,brcmnand
83 enum: [ nand, flash-dma, flash-edu, nand-cache, nand-int-base, iproc-idm, iproc-ext ]
89 - description: NAND CTLRDY interrupt
90 - description: FLASH_DMA_DONE if flash DMA is available
91 - description: FLASH_EDU_DONE if EDU is available
98 - const: flash_dma_done
99 - const: flash_edu_done
103 description: reference to the clock for the NAND controller
110 Some versions of this IP include a write-protect
111 (WP) control bit. It is always available on >=
112 v7.0. Use this property to describe the rare
113 earlier versions of this core that include WP
126 brcm,nand-oob-sector-size:
128 integer, to denote the spare area sector size
129 expected for the ECC layout in use. This size, in
130 addition to the strength and step-size,
131 determines how the hardware BCH engine will lay
132 out the parity bytes it stores on the flash.
133 This property can be automatically determined by
134 the flash geometry (particularly the NAND page
135 and OOB size) in many cases, but when booting
136 from NAND, the boot controller has only a limited
137 number of available options for its default ECC
139 $ref: /schemas/types.yaml#/definitions/uint32
142 - $ref: nand-controller.yaml#
147 const: brcm,nand-bcm63138
155 - const: nand-int-base
160 const: brcm,nand-bcm6368
168 - const: nand-int-base
174 const: brcm,nand-iproc
185 unevaluatedProperties: false
194 nand-controller@f0442800 {
195 compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand";
196 reg = <0xf0442800 0x600>,
198 reg-names = "nand", "flash-dma";
199 interrupt-parent = <&hif_intr2_intc>;
200 interrupts = <24>, <4>;
202 #address-cells = <1>;
206 compatible = "brcm,nandcs";
207 reg = <1>; // Chip select 1
209 nand-ecc-strength = <12>;
210 nand-ecc-step-size = <512>;
212 #address-cells = <1>;
217 nand-controller@10000200 {
218 compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
219 "brcm,brcmnand-v4.0", "brcm,brcmnand";
220 reg = <0x10000200 0x180>,
223 reg-names = "nand", "nand-int-base", "nand-cache";
224 interrupt-parent = <&periph_intc>;
226 clocks = <&periph_clk 20>;
227 clock-names = "nand";
229 #address-cells = <1>;
233 compatible = "brcm,nandcs";
236 nand-ecc-strength = <1>;
237 nand-ecc-step-size = <512>;
239 #address-cells = <1>;