1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 $id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI AM654 MMC Controller
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: mmc-controller.yaml#
19 - const: ti,am654-sdhci-5.1
20 - const: ti,j721e-sdhci-8bit
21 - const: ti,j721e-sdhci-4bit
22 - const: ti,am64-sdhci-8bit
23 - const: ti,am64-sdhci-4bit
25 - const: ti,j7200-sdhci-8bit
26 - const: ti,j721e-sdhci-8bit
28 - const: ti,j7200-sdhci-4bit
29 - const: ti,j721e-sdhci-4bit
43 description: Handles to input clocks
51 # PHY output tap delays:
52 # Used to delay the data valid window and align it to the sampling clock.
53 # Binding needs to be provided for each supported speed mode otherwise the
54 # corresponding mode will be disabled.
56 ti,otap-del-sel-legacy:
57 description: Output tap delay for SD/MMC legacy timing
58 $ref: "/schemas/types.yaml#/definitions/uint32"
62 ti,otap-del-sel-mmc-hs:
63 description: Output tap delay for MMC high speed timing
64 $ref: "/schemas/types.yaml#/definitions/uint32"
68 ti,otap-del-sel-sd-hs:
69 description: Output tap delay for SD high speed timing
70 $ref: "/schemas/types.yaml#/definitions/uint32"
74 ti,otap-del-sel-sdr12:
75 description: Output tap delay for SD UHS SDR12 timing
76 $ref: "/schemas/types.yaml#/definitions/uint32"
80 ti,otap-del-sel-sdr25:
81 description: Output tap delay for SD UHS SDR25 timing
82 $ref: "/schemas/types.yaml#/definitions/uint32"
86 ti,otap-del-sel-sdr50:
87 description: Output tap delay for SD UHS SDR50 timing
88 $ref: "/schemas/types.yaml#/definitions/uint32"
92 ti,otap-del-sel-sdr104:
93 description: Output tap delay for SD UHS SDR104 timing
94 $ref: "/schemas/types.yaml#/definitions/uint32"
98 ti,otap-del-sel-ddr50:
99 description: Output tap delay for SD UHS DDR50 timing
100 $ref: "/schemas/types.yaml#/definitions/uint32"
104 ti,otap-del-sel-ddr52:
105 description: Output tap delay for eMMC DDR52 timing
106 $ref: "/schemas/types.yaml#/definitions/uint32"
110 ti,otap-del-sel-hs200:
111 description: Output tap delay for eMMC HS200 timing
112 $ref: "/schemas/types.yaml#/definitions/uint32"
116 ti,otap-del-sel-hs400:
117 description: Output tap delay for eMMC HS400 timing
118 $ref: "/schemas/types.yaml#/definitions/uint32"
122 # PHY input tap delays:
123 # Used to delay the data valid window and align it to the sampling clock for
124 # modes that don't support tuning
126 ti,itap-del-sel-legacy:
127 description: Input tap delay for SD/MMC legacy timing
128 $ref: "/schemas/types.yaml#/definitions/uint32"
132 ti,itap-del-sel-mmc-hs:
133 description: Input tap delay for MMC high speed timing
134 $ref: "/schemas/types.yaml#/definitions/uint32"
138 ti,itap-del-sel-sd-hs:
139 description: Input tap delay for SD high speed timing
140 $ref: "/schemas/types.yaml#/definitions/uint32"
144 ti,itap-del-sel-sdr12:
145 description: Input tap delay for SD UHS SDR12 timing
146 $ref: "/schemas/types.yaml#/definitions/uint32"
150 ti,itap-del-sel-sdr25:
151 description: Input tap delay for SD UHS SDR25 timing
152 $ref: "/schemas/types.yaml#/definitions/uint32"
156 ti,itap-del-sel-ddr52:
157 description: Input tap delay for MMC DDR52 timing
158 $ref: "/schemas/types.yaml#/definitions/uint32"
163 description: DLL trim select
164 $ref: "/schemas/types.yaml#/definitions/uint32"
168 ti,driver-strength-ohm:
169 description: DLL drive strength in ohms
170 $ref: "/schemas/types.yaml#/definitions/uint32"
179 description: strobe select delay for HS400 speed mode.
180 $ref: "/schemas/types.yaml#/definitions/uint32"
183 description: Clock Delay Buffer Select
184 $ref: "/schemas/types.yaml#/definitions/uint32"
192 - ti,otap-del-sel-legacy
194 unevaluatedProperties: false
198 #include <dt-bindings/interrupt-controller/irq.h>
199 #include <dt-bindings/interrupt-controller/arm-gic.h>
202 #address-cells = <2>;
206 compatible = "ti,am654-sdhci-5.1";
207 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
208 power-domains = <&k3_pds 47>;
209 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
210 clock-names = "clk_ahb", "clk_xin";
211 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
212 sdhci-caps-mask = <0x80000007 0x0>;
214 ti,otap-del-sel-legacy = <0x0>;
215 ti,otap-del-sel-mmc-hs = <0x0>;
216 ti,otap-del-sel-ddr52 = <0x5>;
217 ti,otap-del-sel-hs200 = <0x5>;
218 ti,otap-del-sel-hs400 = <0x0>;
219 ti,itap-del-sel-legacy = <0x10>;
220 ti,itap-del-sel-mmc-hs = <0xa>;
221 ti,itap-del-sel-ddr52 = <0x3>;